Oxide Semiconductor Memory Cell Layout for Dense Low-Power Storage
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving high integration, high operating speed, excellent electrical characteristics, low power consumption, and large memory capacity while maintaining reliability and reducing variation in transistor electrical characteristics.
Innovation Solution
A semiconductor device is designed with a structure that includes multiple transistors and a capacitor, utilizing metal oxides with specific compositions and layered structures to enhance performance. The device also employs a method for manufacturing that minimizes processing steps, allowing for high integration and efficient data storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional semiconductor devices are scaled down to achieve high integration, then memory capacity increases, but electrical characteristics deteriorate and variation increases
Solution Approach 1:
The patent changes the material parameter from conventional semiconductor to metal oxide semiconductor, which fundamentally alters the electrical characteristics. This material parameter change enables maintaining excellent electrical characteristics and low variation even when devices are scaled down for high integration, directly resolving the contradiction between memory capacity and electrical characteristics reliability
Solution Approach 2:
The patent employs composite material structures including metal oxide semiconductor layers combined with specific insulator layers (gate insulator, interlayer insulator) and conductor layers. This composite structure approach enables simultaneous achievement of high integration density and stable electrical characteristics by optimizing the interaction between different materials
2Quantity of substance
If transistor size is reduced to increase integration density, then memory capacity increases, but operating speed decreases
Solution Approach 1:
By changing the semiconductor material parameter to metal oxide semiconductor, the patent maintains high field-effect mobility even in miniaturized transistors. This enables small transistors to operate at high speeds, resolving the contradiction between integration density and operating speed
Solution Approach 2:
The patent utilizes vertical stacking of multiple transistors in the third dimension, allowing high integration density without further reducing transistor size in the planar dimension. This dimensional approach maintains operating speed while achieving high integration
3Use of energy by moving object
If power consumption is reduced to improve energy efficiency, then energy savings increase, but electrical characteristics deteriorate
Solution Approach 1:
The metal oxide semiconductor material parameter change enables transistors with extremely low off-state current, allowing ultra-low power operation. Simultaneously, the material maintains good on-state current, ensuring excellent electrical characteristics are preserved even at low power consumption levels
Data Source
AI summary
A semiconductor device that can be scaled down or highly integrated is provided. The semiconductor device includes a memory cell including first to third transistors and a capacitor. In each of the first to third transistors, the side surfaces of a metal oxide are covered with a source electrode and a drain electrode. The second and third transistors share the metal oxide. The capacitor is provided above the first to third transistors. A conductor including a region functioning as a write bit line is provided to include a region in contact with the top surface and the side surface of one of the source electrode and the drain electrode of the first transistor. A conductor including a region functioning as a read bit line is provided to include a region in contact with the top surface and the side surface of one of the source electrode and the drain electrode of the third transistor. The other of the source electrode and the drain electrode of the first transistor and a gate of the second transistor are electrically connected to one electrode of the capacitor.