Oxide Semiconductor Memory Cell Structure for Refresh-Free Retention
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Solution Overview
Problem
Conventional semiconductor memory devices face challenges in retaining data without power, with volatile devices like DRAM requiring frequent refresh and high power consumption, while non-volatile devices like flash memory suffer from limited write cycles and high voltage requirements.
Innovation Solution
A semiconductor device with a layered structure incorporating a transistor using an oxide semiconductor and another material, allowing for low off-current and long data retention without the need for refresh operations, high-speed data access, and unlimited write cycles by switching between on and off states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a volatile memory device like DRAM is used to store data, then data can be accessed quickly, but the device requires frequent refresh operations and consumes high power
Solution Approach 1:
The invention divides the memory system into two distinct parts: a volatile memory region (DRAM) for frequently accessed data requiring fast access, and a non-volatile memory region for data that needs to be retained without power. This segmentation allows each region to operate optimally without the other's drawbacks, reducing overall power consumption while maintaining fast access speeds for active data.
Solution Approach 2:
The patent introduces a new dimension to memory architecture by stacking different memory types vertically or organizing them in hierarchical layers, allowing simultaneous access to both volatile and non-volatile regions. This dimensional organization enables fast data retrieval from the volatile portion while the non-volatile portion provides persistent storage without requiring continuous refresh operations.
2Duration of action of stationary object
If a non-volatile memory device like flash memory is used to retain data without power, then data holding time is extended, but the device requires high voltage and has limited write cycles
Solution Approach 1:
The invention separates write-intensive operations from read-intensive operations by directing them to different memory regions. The volatile memory portion handles frequent writes with its high write endurance, while the non-volatile memory portion handles data that needs long-term retention. This segmentation prevents the wear and tear of frequent writes from degrading the non-volatile memory's retention capabilities.
Solution Approach 2:
The patent introduces a control mechanism that acts as an intermediary between the host system and the dual memory structure. This intermediary intelligently manages data placement, write operations, and read operations, directing appropriate data to the suitable memory region based on access patterns and data importance, thereby optimizing both write cycle usage and data retention.
3Speed
If a transistor using conventional semiconductor material is used, then high-speed operation is achieved, but the device cannot retain data without power
Solution Approach 1:
The invention merges two types of transistors with different characteristics into a single integrated memory device. Conventional semiconductor transistors provide high-speed operation for active data manipulation, while oxide semiconductor transistors provide non-volatile data retention. The merging of these complementary transistor types enables the memory device to simultaneously achieve fast operation and long-term data retention without power.
Solution Approach 2:
The patent employs composite material structures in the transistor design, combining conventional semiconductor materials (like silicon) with oxide semiconductor materials. This composite approach leverages the high mobility of conventional semiconductors for fast switching and the low off-state current of oxide semiconductors for data retention, achieving both high speed and non-volatile characteristics in a unified device structure.
4Duration of action of stationary object
If a transistor using oxide semiconductor is used, then low off-current and long data retention are achieved, but the device cannot operate at high speed
Solution Approach 1:
The invention divides the transistor population into two segments: conventional semiconductor transistors for high-speed operations requiring fast switching, and oxide semiconductor transistors for data storage requiring low leakage and long retention. This segmentation allows each transistor type to perform its optimal function without compromising overall system performance.
Solution Approach 2:
The patent applies different material qualities to different functional regions of the memory device. High-mobility conventional semiconductor materials are used in regions requiring fast switching (such as access transistors), while low-leakage oxide semiconductor materials are used in regions requiring data retention (such as storage transistors). This local quality optimization ensures each region has the material properties best suited for its specific function.
Data Source
AI summary
Disclosed is a semiconductor device capable of functioning as a memory device. The memory device comprises a plurality of memory cells, and each of the memory cells contains a first transistor and a second transistor. The first transistor is provided over a substrate containing a semiconductor material and has a channel formation region in the substrate. The second transistor has an oxide semiconductor layer. The gate electrode of the first transistor and one of the source and drain electrodes of the second transistor are electrically connected to each other. The extremely low off current of the second transistor allows the data stored in the memory cell to be retained for a significantly long time even in the absence of supply of electric power.