Oxide Semiconductor Memory Cell Stacking for Fast, Compact Arrays
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Solution Overview
Problem
Current semiconductor devices face challenges in miniaturization, circuit area reduction, improved operating and write/read speeds, low power consumption, and reliability, particularly in achieving favorable electrical characteristics and retention characteristics for memory elements.
Innovation Solution
A semiconductor device is designed with multiple sub-memory cells, each comprising a first and second transistor and a capacitor, where the semiconductor layers include oxide semiconductors, with specific atomic ratios for In, M, and Zn, and the gate electrodes are connected to source or drain electrodes, allowing for efficient electrical connections and reduced circuit area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If conventional semiconductor materials and structures are used, then manufacturing process is well-established, but miniaturization and circuit area reduction are limited
Solution Approach 1:
The patent employs a three-dimensional stacked structure where memory cells are arranged in multiple layers vertically. Sub-memory cells are stacked one above another, with interlayer insulating films separating different levels. This vertical stacking enables significant circuit area reduction while maintaining or improving electrical characteristics through controlled layer design and material selection.
Solution Approach 2:
The memory cell is divided into multiple sub-memory cells (first sub-memory cell, second sub-memory cell, etc.), each containing transistors and capacitors that are further segmented into source regions, drain regions, and channel regions. This segmentation allows for optimized electrical characteristics in each segment while achieving overall miniaturization through compact arrangement.
2Speed
If transistor size is reduced for miniaturization, then circuit area decreases, but operating speed and write/read speed deteriorate
Solution Approach 1:
The patent applies different material compositions and structural configurations to different regions within the transistor. The source region, drain region, and channel region have distinct dopant concentrations and material properties optimized for their specific functions. This local quality optimization maintains high operating speed even in miniaturized transistors by ensuring each region performs its function efficiently.
Solution Approach 2:
The patent utilizes controlled doping parameters, including dopant concentration, dopant type, and doping depth, to optimize transistor performance at reduced sizes. By adjusting these parameters locally in different regions, the invention maintains high operating and write/read speeds despite miniaturization of the transistor structure.
3Reliability
If memory cell structure is simplified for manufacturing, then manufacturing precision requirements decrease, but retention characteristics and reliability worsen
Solution Approach 1:
The patent implements a nested structure where sub-memory cells are stacked within a hierarchical arrangement. Each sub-memory cell contains transistors and capacitors that are nested within insulating films and structural layers. This nested design provides natural alignment references between layers, reducing the need for high-precision external alignment while maintaining reliable electrical connections and retention characteristics.
Solution Approach 2:
Interlayer insulating films serve as intermediary layers between different levels of stacked memory cells. These intermediary layers provide both electrical isolation and mechanical support, facilitating easier manufacturing by reducing direct alignment requirements between distant layers while maintaining reliable electrical characteristics through controlled interface design.
Data Source
AI summary
To provide a semiconductor device suitable for miniaturization. To provide a highly reliable semiconductor device. To provide a semiconductor device with improved operating speed.A semiconductor device including a memory cell including first to cth (c is a natural number of 2 or more) sub memory cells, wherein: the jth sub memory cell includes a first transistor, a second transistor, and a capacitor; a first semiconductor layer included in the first transistor and a second semiconductor layer included in the second transistor include an oxide semiconductor; one of terminals of the capacitor is electrically connected to a gate electrode included in the second transistor; the gate electrode included in the second transistor is electrically connected to one of a source electrode and a drain electrode which are included in the first transistor; and when j≥2, the jth sub memory cell is arranged over the j-lth sub memory cell.