Oxide Semiconductor Memory Cell Layout for Low Leakage Density Scaling
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Solution Overview
Problem
Current semiconductor devices, particularly memory devices, face challenges in achieving high reliability, integration density, operating speed, and reduced power consumption, especially with the use of oxide semiconductors like In—Ga—Zn oxide (IGZO) where parasitic capacitance and leakage paths affect performance.
Innovation Solution
The design incorporates a memory device with a specific configuration of oxide layers and transistors where the gate electrodes of adjacent memory elements are closely spaced, with oxide layers extending along the side surfaces of wirings, and the use of indium and zinc-containing oxide layers to minimize parasitic capacitance and enhance transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory elements are closely spaced to increase integration density, then integration density improves, but parasitic capacitance and leakage currents increase
Solution Approach 1:
An oxide layer is introduced as an intermediary substance between closely spaced memory elements and transistor components. This oxide layer acts as a barrier that reduces parasitic capacitance and suppresses leakage currents, enabling high integration density without suffering from the harmful effects of close spacing.
Solution Approach 2:
The patent utilizes changes in the physical and chemical parameters of oxide layers (such as thickness, composition, and crystallinity) to optimize the balance between integration density and parasitic effect suppression. By controlling oxide layer parameters, the device achieves both high integration and low parasitic capacitance.
2Productivity
If transistor size is reduced to increase integration, then integration density improves, but off-state current control becomes more difficult
Solution Approach 1:
The oxide layer serves as a mediator between the gate electrode and the semiconductor channel in miniaturized transistors. This intermediary layer provides excellent interface quality and effective charge trapping, enabling precise control of off-state currents even in highly integrated, miniaturized transistor structures.
Solution Approach 2:
The patent employs composite material structures combining oxide semiconductors with metal gates and oxide insulation layers. This composite approach creates transistors with superior off-state characteristics that maintain reliability even as device dimensions are reduced for higher integration.
3Object-generated harmful factors
If oxide layer thickness is increased to reduce leakage, then leakage current decreases, but device capacitance and area increase
Solution Approach 1:
The patent uses composite oxide structures with multiple layers of different compositions and thicknesses. This composite approach achieves effective leakage suppression through the combined properties of different oxide materials while maintaining overall thin profile and minimizing device area and capacitance.
Data Source
AI summary
A novel memory device is provided. The memory device includes a plurality of first wirings extending in a first direction, a plurality of memory element groups, and an oxide layer extending along a side surface of the first wiring. Each of the memory element groups includes a plurality of memory elements. Each of the memory elements includes a first transistor and a capacitor. A gate electrode of the first transistor is electrically connected to the first wiring. The oxide layer includes a region in contact with a semiconductor layer of the first transistor. A second transistor is provided between the adjacent memory element groups. A high power supply potential is supplied to one or both of a source electrode and a drain electrode of the second transistor.