Oxide Semiconductor Memory Pillars for Low Off-Current Switching
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor devices face challenges in achieving high integration density and performance due to limitations in materials like silicon and polysilicon, which result in high off-current, low electron mobility, and limited switching speed, especially when forming vertical access devices using oxide semiconductor materials.
Innovation Solution
The method involves forming dielectric support structures over conductive line contact structures, with conductive gate structures and dielectric oxide structures within trenches, and forming semiconductive pillars on exposed side surfaces, allowing for the creation of oxide semiconductor pillars that improve electrical properties and reduce off-state current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional silicon or polysilicon materials are used for access device channels, then manufacturing is easier and device structure is simpler, but off-current is high, electron mobility is low, and switching speed is limited
Solution Approach 1:
The patent changes the material parameter from conventional silicon/polysilicon to oxide semiconductor material, which fundamentally alters the electrical properties by providing a larger band gap. This parameter change directly reduces off-current and improves electron mobility, resolving the contradiction between reliability and ease of manufacture by accepting increased processing complexity for superior electrical performance
Solution Approach 2:
The patent employs composite material structures including oxide semiconductor channels combined with specific gate dielectric materials and metal gates. This composite approach allows optimization of each layer's properties to achieve low off-current and high electron mobility while managing the complexity of manufacturing through standardized multi-layer fabrication processes
2Reliability
If oxide semiconductor material is used for access device channels, then off-current is reduced and electron mobility is improved, but device complexity increases due to additional processing steps
Solution Approach 1:
The patent segments the fabrication process into distinct modules: forming oxide semiconductor layers, patterning channel regions, depositing gate dielectrics, and forming metal gates. This segmentation allows each complex step to be independently optimized and controlled, reducing overall fabrication complexity while maintaining the electrical performance benefits of oxide semiconductor materials
Solution Approach 2:
The patent performs preliminary actions by pre-forming oxide semiconductor layers and pre-patterning channel regions before final gate structure assembly. This preliminary preparation simplifies subsequent processing steps and reduces the complexity of the overall fabrication sequence while ensuring proper electrical properties are established early in the process
3Reliability
If conventional etching methods are used to form vertical oxide semiconductor channels, then manufacturing is simpler, but etch chemistries damage the oxide semiconductor material and limit device performance
Solution Approach 1:
The patent introduces intermediary protective layers and carefully selected etch chemistries that act as mediators between the etching process and the oxide semiconductor channel material. These intermediaries protect the channel material from damage while enabling effective pattern transfer, resolving the contradiction between manufacturing simplicity and material integrity by adding controlled intermediate steps
Solution Approach 2:
The patent employs inert atmosphere etching processes that prevent hydrogen-containing plasma damage to the oxide semiconductor material. By creating an inert etching environment, the channel material integrity is preserved while maintaining reasonable manufacturing complexity through established semiconductor fabrication techniques
4Productivity
If feature dimensions are reduced to increase integration density, then device compactness is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent utilizes the unique material properties of oxide semiconductors, particularly their larger band gap and controlled carrier concentrations, to maintain device performance at reduced dimensions. This parameter change in material physics allows scaling to higher integration densities while managing manufacturing precision requirements through material-based performance tolerance
Solution Approach 2:
The patent replaces reliance on purely mechanical/geometric precision with material-property-based control mechanisms. By using oxide semiconductor materials with inherent electrical property stability, the design compensates for dimensional variations, allowing higher integration density without proportionally increasing manufacturing precision requirements
Data Source
AI summary
A method of forming a device comprises forming dielectric structures over other dielectric structures overlying conductive contact structures, the dielectric structures separated from one another by trenches and laterally extending orthogonal to the other dielectric structures and the conductive contact structures. Conductive gate structures are formed on exposed side surfaces of the dielectric structures within the trenches. Dielectric oxide structures are formed on exposed side surfaces of the conductive gate structures within the trenches. Exposed portions of the other dielectric structures are removed to form isolation structures. Semiconductive pillars are formed on exposed side surfaces of the dielectric oxide structures and the isolation structures within the trenches. The semiconductive pillars are in electrical contact with the conductive contact structures. Additional conductive contact structures are formed on upper surfaces of the semiconductive pillars. A device, a memory device, and an electronic system are also described.