Oxide Semiconductor Memory Circuits With Adjustable Memory Regions
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Solution Overview
Problem
Existing semiconductor devices face challenges in sharing memory regions between different types of memory devices, such as main memory and cache memory, due to varying performance requirements, leading to difficulties in compensating for capacity shortfalls and optimizing power consumption and area usage.
Innovation Solution
A semiconductor device with a memory system comprising multiple memory circuits operating at different levels, utilizing oxide semiconductors and a control circuit that adjusts voltage levels and memory capacity allocation based on temperature and usage status, allowing for dynamic changes in memory performance and capacity allocation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate memory devices are used for different memory levels, then each memory device can be optimized for its specific performance requirements, but it becomes difficult to share memory regions and compensate for capacity shortfalls between memory devices
Solution Approach 1:
The patent implements a unified memory controller that can manage multiple memory circuits (first memory circuit with higher access speed and second memory circuit with lower access speed) as a single integrated memory system. This allows the same memory controller to allocate and manage memory regions across different memory circuits dynamically, enabling capacity compensation and region sharing between memory devices while maintaining optimized performance for each memory level.
2Quantity of substance
If memory capacity is increased to meet all requirements, then sufficient storage is available, but power consumption and device area increase
Solution Approach 1:
The patent divides the memory system into multiple memory circuits operating at different speed levels (first memory circuit with higher access speed and second memory circuit with lower access speed). The memory controller dynamically allocates data storage to appropriate memory circuits based on access speed requirements, allowing the system to use only the necessary memory capacity at each performance level, thereby reducing overall power consumption and device area while maintaining sufficient storage capacity.
3Speed
If high-speed memory is used throughout, then access speed is improved, but power consumption and area requirements increase
Solution Approach 1:
The patent applies different memory circuit characteristics to different memory levels based on local performance requirements. The first memory circuit provides high-speed access for frequently accessed data, while the second memory circuit provides lower-speed access for less frequently accessed data. This local differentiation allows the system to achieve high access speed where needed without increasing device area throughout the entire memory system.
Data Source
AI summary
A semiconductor device in which a memory region at each level of a memory device can be changed is provided. The semiconductor device includes a memory device including a first and a second memory circuit and a control circuit. The first memory circuit includes a first capacitor and a first transistor which has a function of holding charges held in the first capacitor. The second memory circuit includes a second transistor, a second capacitor which is electrically connected to a gate of the second transistor, and a third transistor which has a function of holding charges held in the second capacitor. The first and the third transistors each have a semiconductor layer including an oxide semiconductor, a gate, and a back gate. The voltage applied to the back gate of the first or the third transistor is adjusted, whereby the memory region of each of the first and the second memory circuit is changed.