Oxide Semiconductor Memory Circuits With Switchable Memory Regions
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Solution Overview
Problem
Existing semiconductor devices face challenges in sharing memory regions between different types of memory devices, such as main memory and cache memory, due to varying performance requirements, leading to difficulties in compensating for capacity shortfalls and optimizing power consumption and area usage.
Innovation Solution
A semiconductor device with a memory system comprising multiple memory circuits operating at different levels, utilizing oxide semiconductors and a control circuit that adjusts voltage levels and memory capacity allocation based on temperature and usage status, allowing for dynamic switching between memory levels to optimize performance and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If different types of memory devices (main memory, cache memory) are used with different performance characteristics, then each memory type can be optimized for its specific function, but it becomes difficult to share memory regions between them and compensate for capacity shortfalls
Solution Approach 1:
The patent implements a unified memory controller that can manage multiple types of memory devices (main memory and cache memory) through a single control interface. The controller dynamically allocates and shares memory regions between different memory types based on system needs, enabling one memory system to serve multiple functions and compensate for capacity shortfalls across different memory levels.
2Quantity of substance
If memory capacity is increased to compensate for shortfalls, then memory availability improves, but device area increases
Solution Approach 1:
The patent combines main memory and cache memory into a unified memory system with shared control logic and memory regions. By merging previously separate memory systems, the patent achieves higher total memory capacity without proportionally increasing device area, as shared infrastructure (controllers, wiring, control logic) serves multiple memory types simultaneously.
3Speed
If memory performance is optimized for speed, then access time improves, but power consumption increases
Solution Approach 1:
The patent implements dynamic memory management where the system can adjust memory operation modes based on performance requirements. The unified controller can dynamically allocate memory regions between fast cache memory and slower main memory, adjusting the balance between access speed and power consumption in real-time based on system demands and thermal conditions.
4Ease of operation
If multiple memory levels are maintained separately, then each level can operate independently, but the system cannot dynamically allocate memory between levels
Solution Approach 1:
The patent segments memory into different functional levels (cache and main memory) while maintaining unified control. The memory system is divided into operable levels with distinct characteristics, yet the unified controller enables dynamic allocation and sharing of memory regions between segments, allowing independent operation when needed while enabling flexible resource distribution when required.
Data Source
AI summary
A semiconductor device in which a memory region at each level of a memory device can be changed is provided. The semiconductor device includes a memory device including a first and a second memory circuit and a control circuit. The first memory circuit includes a first capacitor and a first transistor which has a function of holding charges held in the first capacitor. The second memory circuit includes a second transistor, a second capacitor which is electrically connected to a gate of the second transistor, and a third transistor which has a function of holding charges held in the second capacitor. The first and the third transistors each have a semiconductor layer including an oxide semiconductor, a gate, and a back gate. The voltage applied to the back gate of the first or the third transistor is adjusted, whereby the memory region of each of the first and the second memory circuit is changed.