Stacked Oxide-Silicon Memory Transistors With Threshold Correction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor devices using oxide semiconductors face challenges in achieving low off-state current, high reliability, and cost-effective manufacturing while maintaining low power consumption and compact size.
Innovation Solution
A semiconductor device structure incorporating a silicon substrate with multiple transistor layers, including a driver circuit and memory cells using metal oxide transistors, where the metal oxide transistors have a novel structure with In, Ga, and Zn composition, and a correction circuit to manage threshold voltage, allowing for efficient data readout and reduced manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If oxide semiconductor transistors are used in memory cells, then off-state current is reduced and power consumption is lowered, but threshold voltage variation affects data readout reliability
Solution Approach 1:
A correction circuit is provided that measures the threshold voltage of the transistor in the memory cell and applies a compensating voltage to correct the threshold voltage variation. This feedback mechanism ensures that data readout reliability is maintained despite variations in transistor characteristics, while still benefiting from the low off-state current properties of oxide semiconductor transistors.
2Volume of moving object
If multiple transistor layers are stacked to reduce device size, then integration density is improved, but manufacturing complexity increases
Solution Approach 1:
The invention stacks multiple transistor layers in the vertical direction (z-axis) to achieve three-dimensional integration. This allows memory cells and correction circuits to be arranged in different layers, reducing the planar footprint while maintaining manufacturability through standardized layer-by-layer fabrication processes.
Solution Approach 2:
The device is divided into multiple functional layers: a first transistor layer for memory cells and a second transistor layer for correction circuits. This segmentation allows each layer to be optimized independently and simplifies the manufacturing process by enabling modular fabrication and assembly.
Data Source
AI summary
A novel semiconductor device is provided. The semiconductor device includes a driver circuit including a plurality of transistors using a silicon substrate for channels, and a first transistor layer and a second transistor layer including a plurality of transistors using a metal oxide for channels. The first transistor layer and the second transistor layer are provided over the silicon substrate layer. The first transistor layer includes a first memory cell including a first transistor and a first capacitor. The first transistor is electrically connected to a first local bit line. The second transistor layer includes a second transistor whose gate is electrically connected to the first local bit line and a first correction circuit electrically connected to the second transistor. The first correction circuit is electrically connected to a first global bit line. The first correction circuit has a function of holding a voltage corresponding to a threshold voltage of the second transistor in the gate of the second transistor.