Oxide Semiconductor Memory Transistors for Dense Vertical Arrays
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Solution Overview
Problem
Conventional microelectronic device configurations face challenges in increasing memory density while managing complex routing paths and improving transistor electrical properties, particularly with polycrystalline silicon materials leading to high off-current and low electron carrier mobility.
Innovation Solution
The use of oxide semiconductive materials, such as zinc tin oxide (ZTO) and indium gallium zinc oxide (IGZO), in channel structures and contact regions, along with specific geometric and material configurations, to enhance memory density and reduce routing congestion in vertical memory arrays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If polycrystalline silicon is used for channel structures, then manufacturing is easier, but electrical properties deteriorate (high off current, low electron carrier mobility)
Solution Approach 1:
The patent changes the material parameter from polycrystalline silicon to oxide semiconductor materials (such as IGZO and ZTO), which fundamentally alters the electrical properties by introducing a larger band gap. This material substitution enables lower off current and higher electron carrier mobility while maintaining compatibility with existing semiconductor manufacturing processes
Solution Approach 2:
The patent employs composite material structures including oxide semiconductor channel layers combined with specific gate dielectric materials and contact structures. The use of indium-containing oxide materials in contact regions creates optimized interfaces that reduce Schottky barriers while maintaining the beneficial properties of oxide semiconductors in the channel
2Quantity of substance
If vertical memory arrays with additional tiers are formed to increase memory density, then memory density improves, but routing paths become complex and congested
Solution Approach 1:
The patent transitions from planar (2D) memory architecture to vertical (3D) memory arrays, stacking multiple tiers of memory cells vertically. This dimensional change allows memory density to increase significantly while the routing complexity is managed through carefully designed three-dimensional interconnect structures that provide efficient electrical access to all memory cells
Solution Approach 2:
The patent divides the vertical memory array into multiple discrete tiers, each with its own conductive structures and staircase configurations. This segmentation allows for modular design and systematic routing strategies, where each tier can be independently addressed and controlled, reducing overall routing complexity
3Reliability
If oxide semiconductor materials are used for channel structures, then electrical properties improve (lower off current), but doping becomes difficult affecting current flow
Solution Approach 1:
The patent employs metal-rich oxide semiconductor materials that can be deposited using simple sputtering or atomic layer deposition processes without requiring complex in-situ doping facilities. The material composition is optimized during deposition to achieve the desired electrical properties directly, eliminating the need for subsequent doping steps
Solution Approach 2:
The patent changes the approach from doping-based conductivity control to composition-based control, where the metal-to-oxide ratio and stoichiometry are precisely controlled during material deposition. This parameter change enables tuning of electrical properties without requiring diffusion or implantation processes
Data Source
AI summary
A transistor comprises a lower contact structure, a channel structure, a dielectric fill structure, and an upper contact structure. The lower contact structure comprises a first oxide semiconductive material. The channel structure contacts the lower contact structure and comprises a second oxide semiconductive material having a smaller atomic concentration of one or more metals than the first oxide semiconductive material. The dielectric fill structure contacts an inner side surface of the channel structure and has a recessed upper surface relative to the channel structure. The upper contact structure comprises a third oxide semiconductive material having a greater atomic concentration of the one or more metals than the channel structure. The upper contact structure comprises a first portion contacting the upper surface of the dielectric fill structure and the inner side surface of the channel structure, and a second portion contacting the upper surface of the channel structure.