Oxide Semiconductor MTJ Memory Cell for High Rewrite Current
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Solution Overview
Problem
The challenge is to design a storage device with highly integrated MTJ (Magnetic Tunnel Junction) devices and transistors that can increase the current required for rewriting data while reducing leakage current and maintaining stable electrical performance, all within a limited cell area, while also minimizing power consumption.
Innovation Solution
The solution involves a storage device architecture that includes a first wiring, a second wiring, and a first memory cell with a first transistor and a first magnetic tunnel junction device, where the transistor has an oxide semiconductor in its channel formation region, and a sense amplifier circuit with a CMOS-type SRAM cell. This architecture includes a precharge circuit and a stacked-layer structure for the magnetic tunnel junction device, allowing for efficient current management and reduced leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the W-width of the transistor is enlarged to increase the current flowing in the MTJ device, then the current required for rewriting data increases, but the leakage current increases
Solution Approach 1:
The transistor channel is segmented into two distinct regions: a first channel region with higher carrier concentration for providing sufficient rewriting current, and a second channel region with lower carrier concentration for minimizing leakage current. This spatial segmentation allows each region to optimize its electrical characteristics independently, resolving the contradiction between requiring high current for data rewriting and maintaining low leakage current.
Solution Approach 2:
Different regions of the transistor channel are assigned different local electrical properties through controlled carrier concentration gradients. The first channel region near the MTJ device has higher carrier concentration to ensure adequate rewriting current, while the second channel region has lower carrier concentration to reduce leakage. This local quality differentiation enables the transistor to simultaneously satisfy both current requirements.
2Power
If the MTJ device is scaled down to reduce the current required for rewriting data, then the current requirement decreases, but the integration density increases making layout design difficult
Solution Approach 1:
Instead of solely relying on MTJ device scaling to reduce current requirements, the invention changes the transistor's electrical parameters by creating a dual-region channel structure. This allows the MTJ device to maintain its scaled-down size for high integration density while the transistor's modified carrier concentration profile compensates by providing sufficient rewriting current, thus resolving the contradiction between current reduction and layout complexity.
3Productivity
If transistors are scaled down to improve LSI performance, then the device performance increases, but the leakage current increases
Solution Approach 1:
The transistor channel employs local quality differentiation with a first channel region having higher carrier concentration for maintaining performance and a second channel region with lower carrier concentration for reducing leakage. This allows scaled-down transistors to achieve both high productivity and low leakage current by optimizing different regions for different functions.
Solution Approach 2:
The channel is segmented into functional regions that can be independently optimized. The segmentation allows the transistor to maintain high performance through the first channel region while simultaneously achieving low leakage through the second channel region, resolving the contradiction that typically arises from transistor scaling.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables increased current for data rewriting, reduced leakage current, and stable electrical performance, thereby achieving high integration and low power consumption in a compact design.
Implementation Method 1
The first transistor includes an oxide semiconductor in its channel formation region
Implementation Method 2
a first magnetic tunnel junction device... Another terminal of the first magnetic tunnel junction device is electrically connected to the second wiring
Data Source
AI summary
A novel storage device is provided. The storage device includes a first wiring, a second wiring, and a first memory cell. The first memory cell includes a first transistor and a first magnetic tunnel junction device. One of a source or a drain of the first transistor is electrically connected to a first wiring. The other of the source or the drain of the first transistor is electrically connected to one terminal of the first magnetic tunnel junction device. Another terminal of the first magnetic tunnel junction device is electrically connected to the second wiring. The first transistor includes an oxide semiconductor in its channel formation region.