Planar Oxide-Nitride Passivation for Crack-Resistant Anneal
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Solution Overview
Problem
Existing passivation layers in semiconductor ICs are prone to stress and cracks during anneal processes, leading to voids and electrical failures due to mismatched thermal expansion coefficients and volumetric shrinkage, particularly at non-planar corners between dielectric material layers.
Innovation Solution
A multi-layer passivation structure is implemented, including a planar nitride layer deposited over a series of oxide layers, with a chemical mechanical polishing process to ensure a level top surface, preventing the nitride layer from extending into oxide layers and reducing stress concentrations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional passivation layer is used, then the semiconductor surface is protected from electrical shorts and chemical contaminants, but the passivation layer is prone to stress and cracks during anneal processes due to mismatched thermal expansion coefficients
Solution Approach 1:
The passivation layer is divided into multiple sub-layers (first passivation layer, second passivation layer, third passivation layer) with different material compositions and thicknesses. Each layer is optimized to handle specific stress conditions, with the lower layers providing mechanical support and the upper layers providing environmental protection, thereby distributing and managing thermal stress throughout the structure.
Solution Approach 2:
The patent employs a composite passivation structure combining different dielectric materials (e.g., silicon oxide, silicon nitride, silicon oxynitride) with distinct mechanical and thermal properties. This composite approach allows each material to contribute its advantageous properties, creating a passivation system that is both protective and resistant to thermal expansion mismatch stresses.
2Strength
If the passivation layer is made thicker to reduce stress, then resistance to thermal expansion mismatch improves, but volumetric shrinkage during anneal increases leading to voids and cracks
Solution Approach 1:
By segmenting the thick passivation structure into multiple thinner layers, each layer experiences reduced volumetric shrinkage during anneal compared to a single thick layer. The segmented structure allows for more uniform stress distribution and prevents the formation of large voids and cracks that would occur in a monolithic thick passivation layer.
Solution Approach 2:
The patent changes the physical and chemical parameters of each passivation layer, including material composition, thickness, and deposition conditions, to optimize the balance between stress resistance and shrinkage control. Each layer is tuned to have specific properties that collectively provide thermal stress management while minimizing void formation.
3Manufacturing precision
If a planarization process is added to create a level surface, then the nitride layer can be deposited uniformly without extending into oxide layers, but the manufacturing complexity increases
Solution Approach 1:
The planarization process is performed as a preliminary step before nitride layer deposition to create a level surface. This preliminary action ensures that subsequent nitride layer deposition is uniform across the substrate, preventing the nitride from extending into oxide layers and maintaining precise layer boundaries, thereby justifying the additional processing step.
4Reliability
If corner structures are eliminated to prevent thermal cracks, then reliability during anneal improves, but the design flexibility for interconnect routing is reduced
Solution Approach 1:
The patent applies different structural characteristics to different regions of the passivation layers. In areas where thermal stress is critical, the layers are designed with continuous, crack-resistant configurations. In areas where routing flexibility is needed, the structure allows for localized variations while maintaining overall integrity, enabling design adaptability without compromising thermal crack resistance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces defect occurrence and improves process yield by eliminating corner structures where thermal cracks can develop, thereby enhancing the reliability of the semiconductor device.
Implementation Method 1
a chemical mechanical polishing process to ensure a level top surface
Implementation Method 2
a planar nitride layer deposited over a series of oxide layers
Implementation Method 3
mismatched thermal expansion coefficients and volumetric shrinkage
Implementation Method 4
mismatched thermal expansion coefficients and volumetric shrinkage
Data Source
AI summary
Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes a redistribution layer including a first conductive feature and a second conductive feature, a first contact feature disposed over and electrically coupled to the first conductive feature, a second contact feature disposed over and electrically coupled to the second conductive feature, and a passivation feature extending from between the first conductive feature and the second conductive feature between the first contact feature and the second contact feature. The passivation feature includes a dielectric feature and a dielectric layer. The dielectric layer is disposed on a planar top surface of the dielectric feature and a composition of the dielectric feature is different from a composition of the dielectric layer.