Semiconductor Chip Passivation Layout for Stable Molding Bonding
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Solution Overview
Problem
Existing semiconductor packages face challenges in achieving high integration and reliable connection of semiconductor chips due to inadequate adhesive force between the molding layer and the semiconductor chip, which affects the stability and performance of the package.
Innovation Solution
The semiconductor chip design includes a passivation layer with an insulating layer and an oxide layer, where the oxide layer has a narrower width than the insulating layer, providing enhanced adhesive force and stability, and a molding layer that contacts the oxide pattern of the passivation layer, ensuring secure bonding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a conventional passivation layer structure is used, then the manufacturing process is simple, but the adhesive force between the molding layer and semiconductor chip is insufficient
Solution Approach 1:
The passivation layer is segmented into multiple distinct layers: a first passivation layer (insulating layer) and a second passivation layer (oxide layer) arranged in sequence. This segmentation allows each layer to perform its specific function - the insulating layer provides electrical insulation while the oxide layer provides adhesive bonding surface for the molding layer, thereby resolving the contradiction between simple structure and sufficient adhesive force.
Solution Approach 2:
The passivation layer uses composite material structure combining different materials with complementary properties. The insulating layer (e.g., silicon nitride) provides high electrical insulation, while the oxide layer (e.g., silicon oxide) provides good adhesion to the molding layer. This composite approach enables the structure to simultaneously achieve electrical insulation and mechanical adhesion without increasing overall complexity.
2Strength
If the oxide layer has the same width as the insulating layer, then the structure is symmetric and simple, but the adhesive force and stability are insufficient
Solution Approach 1:
The oxide layer is designed with asymmetric dimensions relative to the insulating layer. Specifically, the oxide layer has a first width in a first direction (contacting the molding layer) that is greater than its second width in a second direction, while the insulating layer has uniform width. This asymmetric design of the oxide layer creates an optimized bonding interface with the molding layer, enhancing adhesive force and structural stability without significantly complicating the overall structure.
3Productivity
If semiconductor chips are highly integrated with more connection terminals, then the capacity and functionality are improved, but the connection reliability and adhesive force become more challenging to maintain
Solution Approach 1:
The oxide layer is formed in advance as part of the passivation layer structure before the molding layer is applied. This preliminary formation of the adhesive layer ensures that when multiple highly integrated chips are packaged together, the bonding interface is already optimized for strong adhesion, maintaining connection reliability even as integration density and number of connection terminals increase.
Data Source
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AI summary
Provided is a semiconductor chip (100) including a semiconductor substrate (110) including a first surface (110_A) and a second surface (110_UA) opposite to the first surface (110_A), a wiring layer (120) arranged on the first surface (110_A) of the semiconductor substrate (110), a plurality of through electrodes (140) extending from the first surface (110_A) of the semiconductor substrate (110) to the second surface (110_UA) of the semiconductor substrate (110), a plurality of chip pads (130_P) arranged on the second surface (110_UA) of the semiconductor substrate (110) and electrically connected to the plurality of through electrodes (140), and a passivation layer (130) arranged on the second surface (110_UA) of the semiconductor substrate (110) and in contact with side surfaces of the plurality of chip pads (130_P). The passivation layer (130) includes an insulating layer (131) and an oxide layer (132) arranged on the insulating layer (131). The insulating layer (131) includes an insulating pattern having a first width along a horizontal direction. The oxide layer (132) includes a first oxide pattern having a second width along the horizontal direction. The first width is greater than the second width.