Semiconductor Device Manufacturing via Oxide Pattern Extension
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Solution Overview
Problem
As integrated circuits achieve higher integration density, the increased aspect ratio of openings between adjacent floating gates in flash memories leads to the formation of seams and voids during control gate patterning, resulting in reduced gate-coupling ratios and potential side etching.
Innovation Solution
A manufacturing method involving the sequential formation of a conductive layer, oxide layer, and hardmask layer on a substrate, followed by patterning and oxidation to create an extending oxide pattern, which is then removed to form a recess and prevent seams and voids, allowing for a rounded corner on the conductive structure to avoid side etching and enhance gate-coupling ratios.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the distance between adjacent active areas is reduced to increase integration density, then the integration density is improved, but seams and voids are more likely to be formed between adjacent floating gates
Solution Approach 1:
The patent applies preliminary action by forming a mandrel structure with rounded corners before depositing the control gate material. This pre-formed mandrel prevents side etching during control gate patterning, thereby preventing seam and void formation between adjacent floating gates while maintaining high integration density
Solution Approach 2:
The patent uses spheroidality by forming the mandrel with rounded corners instead of sharp edges. This curvature prevents the formation of seams and voids during subsequent patterning steps, as the rounded geometry eliminates stress concentration points and prevents material deficiency at corners
2Quantity of substance
If the aspect ratio of openings between floating gates is increased, then the integration density is improved, but side etching is likely to occur during control gate patterning
Solution Approach 1:
The mandrel structure is formed in advance with dimensions and rounded corners specifically designed to compensate for aspect ratio challenges. This preliminary structure provides a robust template that prevents side etching even when openings have high aspect ratios
Solution Approach 2:
The patent changes the geometric parameters of the mandrel, specifically using rounded corners instead of sharp edges and adjusting the mandrel dimensions. These parameter changes prevent side etching during control gate patterning while maintaining the required high aspect ratio for integration density
3Quantity of substance
If the control gate is formed over floating gates with high aspect ratio openings, then the integration density is improved, but the gate-coupling ratio is reduced
Solution Approach 1:
The mandrel is formed as a preliminary structure with optimized dimensions and rounded corners that ensure proper material coverage during control gate deposition. This prevents gate-coupling ratio reduction by ensuring continuous, defect-free control gate formation over the floating gates
Solution Approach 2:
The rounded corners of the mandrel ensure that control gate material is properly deposited at the corners and edges, preventing gaps and ensuring uniform gate-coupling ratio across the entire structure, even with high aspect ratio openings
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively prevents the formation of seams and voids between adjacent floating gates, increases the gate-coupling ratio, reduces leakage current, and minimizes damage from anisotropic etching, while reducing thermal budget through the use of in-situ steam generation.
Implementation Method 1
An oxidation process is performed, such that a second oxide layer is formed on surfaces of the stacking structure and the first conductive layer. A region of the first conductive layer adjacent to a sidewall of the stacking structure is oxidized, such that an extending oxide pattern is formed.
Data Source
AI summary
A manufacturing method of a semiconductor device includes the following steps. A first conductive layer, a first oxide layer, and a hardmask layer are sequentially formed on a substrate. The hardmask layer and the first oxide layer are patterned to form a stacking structure including a hardmask pattern and a first oxide pattern. An oxidation process is performed, such that a second oxide layer is formed on surfaces of the stacking structure and the first conductive layer, and a region of the first conductive layer adjacent to a sidewall of the stacking structure are oxidized to form an extending oxide pattern. The second oxide layer is removed. The stacking structure is applied as a mask to remove an exposed portion of the first conductive layer and the substrate therebelow, such that a first conductive structure and a recess in the substrate are formed. The stacking structure is removed. The extending oxide pattern is removed.