Oxide Semiconductor Pixel Wiring Layout to Limit TFT Damage
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Solution Overview
Problem
The electrical characteristics of transistors in transparent displays using oxide semiconductors deteriorate due to damage during the manufacturing process, leading to reduced display quality.
Innovation Solution
The display device incorporates a thinner conductive layer for source wiring, which alleviates damage to the oxide semiconductor layer, reducing resistivity and signal delay, and includes a thicker conductive layer for routing, thereby suppressing transistor degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thick conductive layer is used for source wiring, then routing capability is improved, but damage to the oxide semiconductor layer increases
Solution Approach 1:
The conductive layer is designed with non-uniform thickness: thinner in the source wiring region (to reduce damage to oxide semiconductor) and thicker in the routing region (to improve routing capability). This local variation in thickness resolves the contradiction by optimizing each region for its specific function.
2Reliability
If a thick conductive layer is used for source wiring, then routing capability is improved, but signal delay increases
Solution Approach 1:
The conductive layer thickness is optimized locally: thinner in the source wiring region (reducing capacitance and signal delay) and thicker in the routing region (maintaining signal integrity over longer distances).
3Reliability
If a thin conductive layer is used for source wiring, then damage to oxide semiconductor layer is reduced, but routing capability deteriorates
Solution Approach 1:
The conductive layer is designed with spatially varying thickness to satisfy conflicting requirements: thin where it contacts the oxide semiconductor (protecting it) and thick where it performs routing functions (improving manufacturability and signal transmission).
Data Source
AI summary
A display device includes a first pixel including a transistor having an oxide semiconductor layer, a first gate wiring, and a first source wiring. The first gate wiring includes a first part of a first conductive, and extends in a first direction. The first source wiring includes a first part of a second conductive layer and a first part of a third conductive layer connected to the first part of the second conductive layer, and extends in a second direction intersecting the first direction. A thickness of the second conductive layer is thinner than a thickness of the first conductive layer and thinner than a thickness of the third conductive layer.


