Oxide Semiconductor Planar Transistor Layout for Low Parasitic Capacitance
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Solution Overview
Problem
Inverted staggered transistors used in display devices suffer from signal delay due to parasitic capacitance, leading to degraded image quality, especially with increasing screen size and resolution, and occupy more area compared to planar transistors, which have simpler manufacturing processes but less reliable semiconductor characteristics.
Innovation Solution
A semiconductor device with a planar transistor structure incorporating an oxide semiconductor film, a gate insulating film, a gate electrode, and insulating films, where the oxide semiconductor film has regions with different impurity element concentrations and crystallinity, and a capacitor with a conductive film and insulating film structure to reduce parasitic capacitance and enhance electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If an inverted staggered transistor structure is used, then the manufacturing process is simple and manufacturing cost is low, but parasitic capacitance increases causing signal delay and degraded image quality
Solution Approach 1:
The patent inverts the conventional transistor structure by placing the gate electrode at the bottom instead of the top, creating an inverted staggered structure. This inversion reduces the overlap area between the gate electrode and source/drain electrodes, thereby reducing parasitic capacitance and improving signal quality while maintaining manufacturing simplicity
2Ease of manufacture
If an inverted staggered transistor structure is used, then the manufacturing process is simple, but the occupation area increases
Solution Approach 1:
The patent optimizes the spatial arrangement of transistor components by adjusting the vertical stacking configuration in the inverted staggered structure. This dimensional optimization allows for more efficient use of planar space, reducing the overall occupation area while preserving the simplified manufacturing process
3Area of stationary object
If a planar transistor structure is used, then the occupation area is reduced, but semiconductor characteristics stability and reliability are compromised
Solution Approach 1:
The patent employs a composite structure combining multiple functional layers including oxide semiconductor films, gate insulating films, and various insulating films with different material properties. This composite approach enables the planar transistor to achieve both compact area and stable semiconductor characteristics through optimized material combinations and layer configurations
Data Source
AI summary
To provide a semiconductor device including a planar transistor having an oxide semiconductor and a capacitor. In a semiconductor device, a transistor includes an oxide semiconductor film, a gate insulating film over the oxide semiconductor film, a gate electrode over the gate insulating film, a second insulating film over the gate electrode, a third insulating film over the second insulating film, and a source and a drain electrodes over the third insulating film; the source and the drain electrodes are electrically connected to the oxide semiconductor film; a capacitor includes a first and a second conductive films and the second insulating film; the first conductive film and the gate electrode are provided over the same surface; the second conductive film and the source and the drain electrodes are provided over the same surface; and the second insulating film is provided between the first and the second conductive films.