Oxide Semiconductor Power Wiring Layout for High-Frequency Noise Blocking
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Solution Overview
Problem
In integrated circuit processing, high-frequency circuits are prone to malfunction due to high frequency noise components flowing through power source lines, especially in low-power consumption devices like smartphones and tablets.
Innovation Solution
A semiconductor device comprising a transistor with an oxide semiconductor layer, where the source and drain are electrically connected to a wiring supplying power, and the first gate is supplied with a reference potential, with a region overlapping with the wiring to prevent noise components from flowing through the power source line.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a bypass structure is added to prevent noise components from flowing through the power source line, then the reliability of the circuit is improved, but the layout area of the circuit increases
Solution Approach 1:
The invention merges the noise prevention function into the existing transistor structure by making the semiconductor layer overlap with the power supply wiring. This integration allows the same structural elements to serve dual purposes: conducting power supply and preventing noise, thereby avoiding additional layout area while improving circuit reliability
Solution Approach 2:
The invention transitions from a planar two-dimensional layout to a three-dimensional stacked structure where the semiconductor layer is positioned vertically above the power supply wiring. This vertical arrangement in the third dimension enables noise prevention functionality without increasing the horizontal layout area, effectively resolving the contradiction between reliability improvement and area conservation
2Reliability
If the transistor structure is modified to include overlapping region with wiring, then noise prevention capability is improved, but the manufacturing complexity increases
Solution Approach 1:
The overlapping structure between the semiconductor layer and power supply wiring is formed during the initial fabrication stages using standard thin-film deposition and patterning processes. By establishing this geometric relationship early in the manufacturing sequence, the design leverages existing process capabilities rather than requiring additional complex manufacturing steps, thus improving noise prevention without significantly increasing manufacturing complexity
Data Source
AI summary
Malfunctions of a circuit is prevented and the reliability of a semiconductor device using the circuit is improved. The semiconductor device includes a first transistor, a second transistor, a load, and a wiring having a function of supplying a power supply potential to the load. A semiconductor layer of the first transistor includes an oxide semiconductor. A semiconductor layer of the second transistor includes an oxide semiconductor. A source and a drain of the first transistor are electrically connected to the wiring. A first gate of the first transistor is supplied with a reference potential. A source and a drain of the second transistor are supplied with the reference potential. A first gate of the second transistor is electrically connected to the wiring. The semiconductor layer of the first transistor includes a region overlapping with the wiring. The semiconductor layer of the second transistor includes a region overlapping with the wiring.