Oxide Profile Engineering for Transistor Gate Isolation

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Solution Overview

Problem

Sharp active corners at trenched isolation region edges in semiconductor constructions lead to high fringing electric fields, causing parasitic transistors with lower threshold voltage and leakage paths, and thinning of field oxide at corners exacerbates these issues, reducing reliability.

Innovation Solution

A semiconductor processing method involving the formation of a patterned mask, trench creation, lateral recessing of nitride-containing structures, oxidation with hydrogen to form oxide structures, and deposition of insulative material, which results in a desirable oxide profile with a step of at least 50 Å at the field edge, mitigating fringing electric fields and oxide thinning.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If a sharp active corner is formed at the trenched isolation region edge, then the transistor structure can be clearly defined and fabricated, but a high fringing electric field is generated that creates parasitic transistors with lower threshold voltage and causes leakage paths

Engineering Contradiction:
Improvetransistor structure definitionVSAvoidfringing electric field
Core Design Contradiction:
Manufacturing precisionVSObject-generated harmful factors

Solution Approach 1:

The patent applies curvature by forming a recessed corner profile at the active corner region where the field oxide meets the trench isolation. This recessed profile replaces the sharp 90-degree corner with a curved or stepped geometry that has a radius of curvature, thereby reducing the concentration of electric field lines and eliminating the parasitic transistor effect while maintaining precise transistor structure definition

Inventive Principle:
Principle #14Spheroidality (Curvature)

2Reliability

If field oxide is grown to provide isolation, then electrical isolation between adjacent structures is achieved, but thinning of the field oxide occurs at corners under transistor gates reducing reliability

Engineering Contradiction:
Improveelectrical isolationVSAvoidfield oxide thickness uniformity
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent applies local quality by creating a non-uniform field oxide structure with different thicknesses in different regions. Specifically, a thicker field oxide is formed at the corner regions under the transistor gates while maintaining the required isolation thickness in other areas. This localized thickening compensates for the natural thinning effect and ensures uniform electrical characteristics across all transistor gates

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method effectively reduces fringing electric fields and prevents field oxide thinning, enhancing the reliability and performance of transistors by creating a recessed corner profile that alleviates parasitic transistor issues and maintains uniformity across transistor gates.

Implementation Method 1

The substrate is oxidized utilizing an oxidant in the presence of hydrogen to form an oxide structure between the trench and the laterally-recessed mask

Methodology Applied
Scientific EffectOxidation: Oxidation

Data Source

PatentUS7473615B2Semiconductor processing methods
Publication Date: 2009.01.06 MICRON TECHNOLOGY INC
  • US7473615B2 patent drawing
  • US7473615B2 patent drawing
  • US7473615B2 patent drawing

AI summary

The invention includes methods of forming oxide structures under corners of transistor gate stacks and adjacent trenched isolation regions. Such methods can include exposure of a semiconductor material to steam and H2, with the H2 being present to a concentration of from about 2% to about 40%, by volume. An oxide structure formed under the bottom corner of a transistor gate stack can have a bottom surface with a topography that includes a step of at least about 50 Å, and an upper surface directly over the bottom surface and having a topography that is substantially planar. Methodology of the present invention can be utilized to form semiconductor constructions suitable for incorporation into highly integrated circuitry. The highly integrated circuitry can be incorporated into electronic systems, and can, for example, be utilized in processors and/or memory storage devices.