Oxide Semiconductor Resistance Profiling for High On-State Current
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving high on-state current, high frequency characteristics, reliability, miniaturization, and low power consumption, particularly in retaining data and enabling high-speed data writing while maintaining design flexibility and reducing power consumption.
Innovation Solution
A semiconductor device structure comprising multiple oxide layers with specific resistance profiles and dopant distribution, along with insulator and conductor configurations, is developed to enhance on-state current, frequency characteristics, and reliability, allowing for miniaturization and high integration while reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If conventional semiconductor materials and structures are used, then manufacturing process is simple, but on-state current is insufficient and frequency characteristics are poor
Solution Approach 1:
The patent applies local quality by creating distinct regions within the semiconductor layer with different properties. Specifically, it forms a first semiconductor layer with a first conductivity type and a second semiconductor layer with a second conductivity type, where each layer has locally optimized electrical characteristics. This allows high on-state current in conductive regions while maintaining the overall device structure
Solution Approach 2:
The patent employs composite materials by combining different semiconductor materials with complementary properties. It uses a first semiconductor material forming a first semiconductor layer and a second semiconductor material forming a second semiconductor layer, creating a composite structure that leverages the advantages of each material to achieve both high on-state current and improved frequency characteristics
2Area of moving object
If device size is reduced for miniaturization, then integration density increases, but achieving high on-state current becomes more difficult
Solution Approach 1:
The patent applies local quality by creating highly conductive localized regions through the combination of doped semiconductor layers. The first and second semiconductor layers are configured to provide localized high conductivity paths, enabling high on-state current in miniaturized devices. This allows the device to maintain small overall area while achieving high current density in specific regions
Solution Approach 2:
The patent employs parameter changes by adjusting the conductivity type and doping levels of different semiconductor layers. By changing the electrical parameters (conductivity type, carrier concentration) of the first and second semiconductor layers, the device achieves high on-state current in a compact structure, resolving the contradiction between miniaturization and current capability
3Use of energy by moving object
If power consumption is reduced, then energy efficiency improves, but data retention capability and high-speed writing become challenging
Solution Approach 1:
The patent applies segmentation by dividing the semiconductor device into functionally distinct first and second semiconductor layers with different conductivity types. This segmentation allows independent optimization of different functions: one layer can be optimized for low-power operation while the other maintains data retention capability, enabling the device to achieve both low power consumption and reliable data storage
Data Source
AI summary
A semiconductor device with a high on-state current is provided. The semiconductor device includes a first oxide, a second oxide over the first oxide, a third oxide over the second oxide, a first insulator over the third oxide, a conductor over the first insulator, a second insulator in contact with the second oxide and the third oxide, and a third insulator over the second insulator; the second oxide includes first region to fifth regions; the resistance of the first region and the resistance of the second region are lower than the resistance of the third region; the resistance of the fourth region and the resistance of the fifth region are lower than the resistance of the third region and higher than the resistance of the first region and the resistance of the second region; and the conductor is provided over the third region, the fourth region, and the fifth region to overlap with the third region, the fourth region, and the fifth region.