Oxide Semiconductor Selection Transistors for NAND Flash Memory
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Solution Overview
Problem
NAND flash memory devices experience write errors due to slight leakage current in selection transistors and require additional control circuits to maintain the off-state of selection transistors, leading to increased device size and complexity.
Innovation Solution
Incorporating oxide semiconductor layers for the channel regions of selection transistors in NAND flash memory devices, which significantly reduces off-state current and eliminates the need for additional control circuits by ensuring accurate data retention without leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional selection transistors are used in NAND flash memory, then the device can operate with standard transistor structures, but leakage current occurs in the selection transistors causing write errors
Solution Approach 1:
The patent changes the material parameter of the selection transistor channel from conventional semiconductor to oxide semiconductor, which fundamentally alters the electrical characteristics to achieve ultra-low leakage current while maintaining reliable data retention
2Reliability
If additional control circuits are added to maintain the off-state of selection transistors, then write errors can be prevented, but the device size increases
Solution Approach 1:
The oxide semiconductor selection transistors inherently maintain their off-state with minimal leakage current without requiring external control circuits, making the system self-sufficient and eliminating additional size-increasing components
Solution Approach 2:
By changing the transistor material to oxide semiconductor, the patent achieves such low leakage current that complex control circuits become unnecessary, thereby preventing write errors while maintaining compact device size
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The use of oxide semiconductor layers in selection transistors minimizes write errors and reduces device size by eliminating the need for additional control circuits, enhancing integration and reliability.
Implementation Method 1
a channel region of each of the first selection transistor and the second selection transistor is formed in an oxide semiconductor layer
Data Source
AI summary
A memory device in which a write error can be prevented is provided. The memory device includes a NAND cell unit including a plurality of memory cells connected in series, a first selection transistor connected to one of terminals of the NAND cell unit, a second selection transistor connected to the other of the terminals of the NAND cell unit, a source line connected to the first selection transistor, and a bit line which intersects with the source line and is connected to the second selection transistor. In the memory device, a channel region of each of the first selection transistor and the second selection transistor is formed in an oxide semiconductor layer.