Oxide Semiconductor 2T-0C Memory Cell for Leakage Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current Dynamic Random Access Memory (DRAM) structures, particularly the 1T-1C Si semiconductor-based structure, face challenges in performance improvement due to trade-offs between leakage current and capacity, leading to low memory transfer performance and increased power consumption.
Innovation Solution
A semiconductor device with a vertically-stacked memory cell transistor based on an oxide semiconductor, featuring a 2T-0C structure where the read transistor acts as a capacitor, reducing the need for a separate capacitor and optimizing the cell structure for improved integration and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the 1T-1C structure is used to increase memory capacity through miniaturization, then the area per cell is reduced, but leakage current increases and power consumption increases
Solution Approach 1:
The patent merges the read transistor and capacitor into a single integrated structure where the read transistor's source/drain region serves as the storage node, eliminating the need for a separate capacitor and reducing overall cell area while maintaining functionality
Solution Approach 2:
The read transistor performs multiple functions: it acts as both the read operation transistor and the storage capacitor, enabling data retention and read operations with a single component that serves dual purposes
2Productivity
If the 1T-1C structure is miniaturized to increase integration density, then more cells fit per chip, but leakage current increases requiring more frequent refresh operations
Solution Approach 1:
By combining the read transistor and capacitor into one integrated unit, the patent reduces the number of interfaces and connections that could be sources of leakage, thereby improving data retention reliability while maintaining high integration density
3Quantity of substance
If a separate capacitor is included in the 1T-1C structure, then data storage capacity is maintained, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent extracts the capacitor function from being a separate physical component and integrates it into the read transistor's source/drain region, eliminating the need for a distinct capacitor structure while preserving storage capacity
Solution Approach 2:
The storage function previously requiring a separate capacitor is merged with the read transistor structure, creating a unified 2T-0C cell that reduces manufacturing steps and structural complexity
Data Source
AI summary
Provided is a semiconductor device including a substrate, a first transistor on the substrate, an interlayer insulating layer covering the first transistor, a second transistor on the interlayer insulating layer, and a storage node contact passing through the interlayer insulating layer, and connecting any one of source/drain electrodes of the first transistor and a gate electrode of the second transistor, wherein a first channel pattern of the first transistor may include an n-type oxide transistor, and a second channel pattern of the second transistor may include an p-type oxide transistor.