Oxide Semiconductor Memory Cell with Back Gate Transistors
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Solution Overview
Problem
Current semiconductor memory devices face challenges in achieving high reliability, large storage capacity, small area occupation, and low production costs, particularly in using oxide semiconductor transistors which require advanced configurations to enhance data retention and writing efficiency.
Innovation Solution
A NAND memory device design incorporating oxide semiconductor transistors with back gates, where each memory cell includes a writing transistor and a reading transistor, allowing for reduced storage capacitor size or elimination, and a specific wiring configuration that enables efficient data writing and reading operations without the need for high voltage or frequent erasing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If oxide semiconductor transistors are used in memory cells, then data retention and reliability are improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The memory cell is divided into multiple transistor components (writing transistor with oxide semiconductor, reading transistor, storage capacitor) with distinct functions. The writing transistor handles data storage with high reliability, while the reading transistor handles data retrieval, separating concerns and managing complexity through functional segmentation
Solution Approach 2:
The oxide semiconductor transistor serves multiple functions: it acts as both the writing transistor for data storage and can function as the reading transistor when configured with a back gate. This multi-functionality reduces the total number of components needed while maintaining high reliability data retention
2Area of moving object
If storage capacitor size is reduced or eliminated in memory cells, then area occupation is reduced, but data retention capability may be compromised
Solution Approach 1:
The invention extracts the data retention function from the traditional storage capacitor by using the oxide semiconductor transistor's inherent low off-state current characteristic. The transistor itself becomes the data holding element, eliminating or reducing the need for a separate storage capacitor while maintaining data retention capability
Solution Approach 2:
The invention changes the key parameter of off-state current to an extremely low level by using oxide semiconductor material. This parameter change allows the transistor to hold data without requiring a large storage capacitor, as the minimal leakage current naturally preserves data over time, enabling area reduction while maintaining reliability
3Productivity
If multiple transistors are included in each memory cell, then data writing and reading efficiency are improved, but manufacturing cost and device area increase
Solution Approach 1:
The invention merges the function of the storage element with the writing transistor by using the oxide semiconductor transistor's gate as both the control terminal and the data storage node. This combining of functions reduces the number of separate components that need to be manufactured and connected, lowering manufacturing complexity and cost while maintaining efficient data writing capability
Solution Approach 2:
The oxide semiconductor transistor with back gate configuration serves as a universal component that can perform both writing and reading operations. This multi-functionality reduces the total transistor count per memory cell, thereby reducing manufacturing steps, material usage, and production costs while maintaining high writing and reading efficiency
Data Source
AI summary
A memory device with large storage capacity is provided. A NAND memory device includes a plurality of connected memory elements each provided with a writing transistor and a reading transistor. An oxide semiconductor is used in a semiconductor layer of the writing transistor, whereby a storage capacitor is not necessary or the size of the storage capacitor can be reduced. The reading transistor includes a back gate. When a reading voltage is applied to the back gate, data stored in the memory element is read out.