Oxide Semiconductor Transistor Base Insulating Layer Capacitance
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Solution Overview
Problem
Transistors using oxide semiconductors face reliability issues due to fluctuations in threshold voltage during bias-temperature stress tests, primarily attributed to charge trapping at the interface between the substrate and insulating layers, leading to unstable electrical characteristics.
Innovation Solution
A semiconductor device with an insulating layer of sufficient thickness is introduced, specifically a base insulating layer or protective insulating layer, to reduce capacitance per unit area and increase the physical distance between the oxide semiconductor layer and the substrate or surface, thereby minimizing charge trapping and fluctuation in threshold voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an insulating layer with sufficient thickness is formed to reduce capacitance and increase physical distance from the substrate, then reliability and electrical characteristic stability are improved, but device complexity and manufacturing process complexity increase
Solution Approach 1:
The insulating layer is divided into multiple distinct layers (base insulating layer, gate insulating layer, and protective insulating layer) with different functions and thickness requirements. The base insulating layer provides mechanical support and electrical isolation from the substrate, the gate insulating layer enables gate control, and the protective insulating layer prevents charge trapping at the top surface. This segmentation allows each layer to be optimized independently for its specific function while collectively solving the reliability problem.
Solution Approach 2:
The thick base insulating layer acts as an intermediary between the substrate and the oxide semiconductor layer, physically separating the semiconductor from the substrate interface where charge trapping occurs. This intermediary layer increases the physical distance and reduces the capacitance coupling, thereby suppressing the adverse effects of substrate interface charges on the transistor's electrical characteristics.
2Reliability
If the insulating layer thickness is increased to suppress charge trapping effects, then threshold voltage stability is improved, but manufacturing cost and process time increase
Solution Approach 1:
The base insulating layer is formed with sufficient thickness before depositing the oxide semiconductor layer and other functional layers. This preliminary action ensures that the charge trapping suppression capability is established early in the manufacturing process, preventing any potential electrical characteristic fluctuations from the substrate interface before they can affect subsequent processing steps or device performance.
Solution Approach 2:
The thickness of the base insulating layer is specifically controlled to achieve a capacitance per unit area of lower than or equal to 2×10^-4 F/m^2, which is the critical parameter for suppressing charge trapping effects. By changing this physical parameter (thickness) to meet the specified capacitance requirement, the patent achieves threshold voltage stability without unnecessarily increasing overall device complexity or manufacturing time.
3Reliability
If a thick insulating layer is used to increase physical distance from the substrate, then charge trapping effects are reduced, but capacitance per unit area decreases which may affect gate control efficiency
Solution Approach 1:
The insulating system is segmented into the thick base insulating layer for charge trapping suppression and the separate gate insulating layer for gate control. The base insulating layer provides the necessary thickness for reducing capacitance and suppressing substrate interface effects, while the gate insulating layer (with appropriate thickness and dielectric constant) ensures efficient gate control of the oxide semiconductor channel.
Solution Approach 2:
The patent optimizes the parameters of different insulating layers independently. The base insulating layer thickness is optimized for charge trapping suppression (capacitance ≤ 2×10^-4 F/m^2), while the gate insulating layer parameters (thickness, dielectric constant) are optimized for gate control efficiency. This parameter optimization across different layers resolves the contradiction between charge trapping suppression and gate control efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The implementation of a thick insulating layer suppresses adverse effects such as charge trapping, resulting in stable electrical characteristics and enhanced reliability of the semiconductor device by reducing fluctuations in threshold voltage during stress tests.
Implementation Method 1
an insulating layer having a sufficient thickness is formed as an insulating layer which faces a gate insulating layer with an oxide semiconductor layer interposed therebetween... specifically, referred to as an insulating layer having a thickness in which capacitance per unit area is lower than or equal to 2×10−4 F/m2
Data Source
AI summary
Disclosed is a semiconductor device with a transistor in which an oxide semiconductor is used. An insulating layer on a back channel side of the oxide semiconductor layer has capacitance of lower than or equal to 2×10−4 F/m2. For example, in the case of a top-gate transistor, a base insulating layer has capacitance of lower than or equal to 2×10−4 F/m2, whereby the adverse effect of an interface state between the substrate and the base insulating layer can be reduced. Thus, a semiconductor device where fluctuation in electrical characteristics is small and reliability is high can be manufactured.