Oxide Semiconductor Device With Carrier Density Gradient
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Solution Overview
Problem
Current semiconductor devices face challenges in miniaturization, high integration, productivity, design flexibility, and electrical characteristics, with complex manufacturing processes and large areas, while also requiring improved data retention and high-speed data writing capabilities.
Innovation Solution
A semiconductor device structure incorporating a first oxide with specific regions and insulators, conductors, and capacitors, where the first oxide includes In, M (Al, Ga, Y, or Sn), and Zn, with a carrier density gradient, and insulators containing aluminum and hafnium, to enhance carrier mobility and reduce leakage current, allowing for miniaturization and high integration while simplifying the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional semiconductor devices are miniaturized and highly integrated, then device density and functionality are improved, but manufacturing complexity and process difficulty increase
Solution Approach 1:
The semiconductor device is divided into distinct functional regions within the first oxide layer: a channel formation region with lower carrier density for transistor operation, and source/drain regions with higher carrier density for current conduction. This segmentation allows each region to be optimized independently while maintaining overall device functionality and simplifying the manufacturing process.
Solution Approach 2:
Different regions of the first oxide are assigned different carrier densities to perform different functions. The channel formation region has lower carrier density (1×10^16 to 1×10^18 atoms/cm³) for effective transistor switching, while source/drain regions have higher carrier density (1×10^19 to 1×10^21 atoms/cm³) for low-resistance current flow. This local quality differentiation enables high device density without proportionally increasing manufacturing complexity.
2Loss of energy
If oxide semiconductor layers are used to reduce leakage current, then power consumption is reduced, but carrier mobility and electrical characteristics may be compromised
Solution Approach 1:
The carrier density in the first oxide is precisely controlled within specific ranges: lower carrier density (1×10^16 to 1×10^18 atoms/cm³) in the channel formation region to minimize leakage current and power consumption, while higher carrier density (1×10^19 to 1×10^21 atoms/cm³) in source/drain regions to ensure adequate current conduction and maintain electrical characteristics.
Solution Approach 2:
The device uses a composite structure with the first oxide (In-M-Zn oxide with specific carrier density) as the semiconductor layer, combined with insulating layers (including aluminum oxide and hafnium oxide) and conductive layers. This composite material approach enables simultaneous achievement of low leakage current through the oxide semiconductor's inherent properties and good electrical characteristics through the composite structure.
3Area of stationary object
If device area is reduced for miniaturization, then integration density is improved, but manufacturing precision and electrical characteristics become more difficult to maintain
Solution Approach 1:
The first oxide layer is formed with predetermined carrier density distributions before subsequent processing steps. The channel formation region is pre-configured with lower carrier density (1×10^16 to 1×10^18 atoms/cm³) and source/drain regions with higher carrier density (1×10^19 to 1×10^21 atoms/cm³), establishing the electrical characteristics foundation early in the manufacturing process. This preliminary action enables miniaturization while maintaining manufacturing precision and electrical characteristics control.
Data Source
AI summary
A semiconductor device including a first oxide including a first region and a second region adjacent to each other and a third region and a fourth region with the first region and the second region sandwiched between the third region and the fourth region, a second oxide over the first region, a first insulator over the second oxide, a first conductor over the first insulator, a second insulator over the second oxide and on side surfaces of the first insulator and the first conductor, a third insulator over the second region and on a side surface of the second insulator, a second conductor over the second region with the third insulator positioned between the second region and the second conductor and on the side surface of the second insulator with the third insulator positioned between the side surface of the second insulator and the second conductor, and a fourth insulator covering the first oxide, the second oxide, the first insulator, the first conductor, the second insulator, the third insulator, and the second conductor and in contact with the third region and the fourth region.