Oxide Semiconductor Contact Hole Resistivity Control
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Solution Overview
Problem
The existing manufacturing processes for thin-film transistors with oxide semiconductor layers face challenges in achieving low resistivity on the inner walls of contact holes, leading to high contact resistance and defects, particularly when using polycrystalline semiconductor layers.
Innovation Solution
The use of an oxide semiconductor layer, such as indium gallium zinc oxide (IGZO), where defects on the inner walls of etched apertures function as donors, allowing for low resistivity and enabling effective contact formation between the semiconductor layer and electrodes, along with specific annealing processes in oxidizing and reducing atmospheres to control resistivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If polycrystalline semiconductor layers are used to form contact holes, then manufacturing is easier, but high contact resistance and defects occur on inner walls
Solution Approach 1:
The patent changes the material parameter from polycrystalline semiconductor to oxide semiconductor, which fundamentally alters the electrical properties of the contact hole inner walls. This material substitution transforms the inner wall from a high-resistance surface to a low-resistance surface, simultaneously achieving ease of manufacture and low contact resistance.
Solution Approach 2:
The patent converts the previously harmful effect (high resistance on contact hole inner walls) into a beneficial effect by utilizing the unique properties of oxide semiconductors. The inner wall, which was previously a source of defects and high resistance, becomes a low-resistance conductive path that improves contact quality.
2Reliability
If oxide semiconductor layer is used, then contact resistance is reduced, but manufacturing precision is required for annealing processes
Solution Approach 1:
The annealing process is segmented into two distinct stages: oxidation annealing to form high-resistance channel regions, and reduction annealing to form low-resistance source/drain regions. This segmentation allows precise control over the electrical properties of different regions within the oxide semiconductor layer.
Solution Approach 2:
The patent applies different thermal treatments to different regions of the oxide semiconductor layer. The channel region undergoes oxidation annealing to achieve high resistance, while the source and drain regions undergo reduction annealing to achieve low resistance. This local differentiation of treatment conditions creates the desired electrical property distribution.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces contact resistance and eliminates defects, enabling efficient formation of low-resistivity source and drain regions while maintaining high resistivity in the channel region, improving the overall performance of thin-film transistors.
Implementation Method 1
annealing processes in oxidizing and reducing atmospheres to control resistivity
Implementation Method 2
annealing processes in oxidizing and reducing atmospheres to control resistivity
Implementation Method 3
annealing processes in oxidizing and reducing atmospheres to control resistivity
Implementation Method 4
annealing processes in oxidizing and reducing atmospheres to control resistivity
Data Source
AI summary
According to one embodiment, a semiconductor device includes contact holes passing through a source region of a drain region of an interlayer insulating film and oxide semiconductor layer to reach an insulating substrate, wherein a source electrode and a drain electrode are formed inside the contact holes, respectively.