Oxide Semiconductor DRAM Plate Line Voltage Control
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Solution Overview
Problem
Existing dynamic random access memory (DRAM) devices face challenges in maintaining high data retention performance, particularly during precharge, due to leakage currents caused by insufficient reverse bias between the gate and source of the cell transistor.
Innovation Solution
The memory device incorporates a transistor with an oxide semiconductor and a capacitor, where the potential of the plate line is set to the power supply voltage Vdd during precharge, thereby increasing the reverse bias between the gate and source of the cell transistor, reducing leakage currents, and enhancing data retention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the plate line potential is not set to Vdd during precharge, then the device complexity is reduced, but leakage currents increase and data retention performance deteriorates
Solution Approach 1:
The patent applies parameter changes by setting the plate line potential to Vdd during precharge operations. This voltage parameter change increases the reverse bias between gate and source of the cell transistor, thereby suppressing leakage currents and improving data retention performance without requiring fundamental structural modifications to the memory device
2Object-generated harmful factors
If the reverse bias between gate and source is increased during precharge, then leakage currents are suppressed, but the use of energy increases due to additional voltage control
Solution Approach 1:
The patent implements periodic action by applying the Vdd potential to the plate line only during specific precharge operations rather than continuously. This selective voltage application suppresses leakage currents when needed while minimizing energy consumption by maintaining the plate line at lower potentials during normal operational modes
Solution Approach 2:
The patent changes the voltage parameter of the plate line dynamically based on operational mode. During precharge, the plate line potential is set to Vdd to suppress leakage; during other operations, it operates at standard potentials. This parameter change approach reduces overall energy consumption while effectively controlling leakage currents when required
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly improves data retention performance by suppressing leakage currents and allowing the memory device to maintain data integrity even during precharge, which is critical for maintaining data in idle states like the Maximum Power Saving Mode (MPSM).
Implementation Method 1
increasing the reverse bias between the gate and source of the cell transistor, reducing leakage currents
Data Source
AI summary
A memory device includes a transistor, a capacitor, a plate line, and a bit line. The transistor includes an oxide semiconductor and includes a first end, a second end, and a gate. The capacitor includes a third end and a fourth end. The fourth end is coupled to the second end. The plate line is coupled to the third end. The bit line is coupled to the first end. A second voltage lower than a first voltage is applied to the plate line during a first period over which the first voltage is applied to the gate. A fourth voltage higher than the second voltage is applied to the plate line during at least a part of a second period over which a third voltage lower than the first voltage is applied to the gate.