Oxide Semiconductor DRAM Cell With Stacked Capacitors
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Solution Overview
Problem
Dynamic random access memory (DRAM) devices face challenges in increasing storage capacity per unit area and reducing power consumption due to short retention periods and inefficient multilevel data storage, primarily attributed to high off-state current in silicon-based transistors and limitations in capacitor design.
Innovation Solution
The use of a semiconductor memory device with a transistor having a channel formed in an oxide semiconductor film and multiple capacitors with different capacitances, where the transistor's off-state current is minimized, allowing for extended retention periods and reduced refresh operations, enabling a multilevel memory cell with increased storage capacity and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a transistor with channel in silicon substrate is used, then the device can be manufactured with conventional processes, but the off-state current is about 1 nA which causes short retention period requiring frequent refresh operations
Solution Approach 1:
The invention changes the material parameter of the transistor channel from silicon to oxide semiconductor, which fundamentally alters the off-state current characteristics. This material substitution enables retention periods of 100 seconds or more while maintaining compatibility with conventional semiconductor manufacturing processes
Solution Approach 2:
The invention employs composite material structure combining oxide semiconductor layer with conventional semiconductor substrates and insulation layers. This composite approach allows achieving ultra-low off-state current characteristics while maintaining manufacturability through established fabrication techniques
2Device complexity
If one transistor and one capacitor are used per memory cell, then the device structure is simple and manufacturing is easy, but the storage capacity per unit area is limited
Solution Approach 1:
The invention introduces stacked capacitor structures extending in the vertical dimension, allowing multiple storage nodes to share a single transistor. This three-dimensional arrangement increases storage capacity per unit area without proportionally increasing device complexity
Solution Approach 2:
The invention makes a single transistor serve multiple functions by controlling multiple stacked capacitors. The transistor acts as a shared switch for multiple storage elements, reducing the overall number of transistors needed and simplifying the cell structure while increasing density
3Quantity of substance
If multilevel memory cell is implemented with multiple capacitors, then storage capacity increases, but the retention period becomes shorter and refresh operations increase
Solution Approach 1:
The invention changes the transistor material parameter to oxide semiconductor, which provides ultra-low off-state current that maintains retention period even when multiple capacitors are stacked. This material parameter change enables multilevel storage with extended retention times
4Reliability
If frequent refresh operations are performed to maintain data, then data integrity is maintained, but power consumption increases significantly
Solution Approach 1:
The invention changes the transistor material to oxide semiconductor with ultra-low off-state current, extending retention period to 100 seconds or more. This parameter change reduces refresh frequency and consequently lowers power consumption while maintaining data integrity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly extends the retention period of electric charges, reduces the frequency of refresh operations, and allows for the downsizing of memory cells, thereby increasing storage capacity per unit area while minimizing power consumption.
Implementation Method 1
a transistor having a channel formed in an oxide semiconductor film... The loss of electric charges from a capacitor is caused by off-state current of a transistor... Since the off-state current flows, electric charges stored in a capacitor are lost with time
Data Source
AI summary
To increase a storage capacity of a memory module per unit area, and to provide a memory module with low power consumption, a transistor formed using an oxide semiconductor film, a silicon carbide film, a gallium nitride film, or the like, which is highly purified and has a wide band gap of 2.5 eV or higher is used for a DRAM, so that a retention period of potentials in a capacitor can be extended. Further, a memory cell has n capacitors with different capacitances and the n capacitors are each connected to a corresponding one of n data lines, so that a variety of the storage capacitances can be obtained and multilevel data can be stored. The capacitors may be stacked for reducing the area of the memory cell.