Oxide Semiconductor DRAM Stacked Memory Cells Sense Amplifiers
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving low power consumption and reduced area while maintaining effective data holding capabilities and refresh operation intervals, particularly in dynamic random access memory (DRAM) where off-state current is significant.
Innovation Solution
The semiconductor device incorporates a cell array with memory cells and sense amplifiers, utilizing oxide semiconductor transistors with a stacked structure to minimize off-state current, share wirings to reduce parasitic capacitance, and optimize the layout for reduced area and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional transistors are used in DRAM, then the device can operate with standard manufacturing processes, but the off-state current is significant leading to frequent refresh operations and higher power consumption
Solution Approach 1:
The patent changes the material parameter of the transistor from conventional semiconductor to oxide semiconductor, which fundamentally alters the off-state current characteristics. This material parameter change enables extremely low off-state current, directly reducing power consumption while maintaining data holding capability through longer refresh intervals.
2Area of stationary object
If memory cells and sense amplifiers are placed in the same layer, then the device layout is simplified, but the area occupied by the device increases
Solution Approach 1:
The patent transitions from a two-dimensional planar layout to a three-dimensional stacked structure. Memory cells are positioned in a first layer and sense amplifiers in a second layer vertically above, utilizing the vertical dimension to reduce the horizontal footprint. This dimensional change directly reduces device area while the wiring interconnects the two layers to maintain functional simplicity.
3Loss of energy
If separate wirings are provided for each memory cell connection, then signal integrity is maintained, but parasitic capacitance increases reducing device efficiency
Solution Approach 1:
The patent merges wiring resources by having multiple memory cells share common word lines and bit lines. This consolidation reduces the total number of separate wirings, thereby reducing parasitic capacitance and energy loss while maintaining signal integrity through proper wiring design and timing control in the stacked memory architecture.
Data Source
AI summary
A semiconductor device with low power consumption or a semiconductor device with a reduced area is provided. The semiconductor device includes a cell array including a first memory cell and a second memory cell; and a sense amplifier circuit including a first sense amplifier and a second sense amplifier. The cell array is over the sense amplifier circuit. The first sense amplifier is electrically connected to the first memory cell through a first wiring BL. The second sense amplifier is electrically connected to the second memory cell through a second wiring BL. The first sense amplifier and the second sense amplifier are electrically connected to a wiring GBL. The sense amplifier circuit is configured to select one of a potential of the first wiring BL and a potential of the second wiring BL and output the selected potential to the wiring GBL.