Oxide Semiconductor Trench Transistor with Dual Gate
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving miniaturization and high integration while maintaining favorable electrical characteristics, particularly in transistors and capacitors, due to limitations in carrier mobility and impurity diffusion prevention.
Innovation Solution
A semiconductor device is designed with a dual-gate transistor structure and a capacitor configuration, utilizing oxide semiconductor layers with varying electron affinities and high impurity barrier insulating layers to enhance carrier mobility and prevent impurity diffusion, including a specific trench structure and layer stacking to increase capacitance without increasing device size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If oxide semiconductor layers are stacked to increase carrier mobility, then electrical characteristics are improved, but device complexity increases
Solution Approach 1:
The semiconductor layer is segmented into multiple oxide semiconductor layers (first oxide semiconductor layer, second oxide semiconductor layer, third oxide semiconductor layer) with different electron affinities. Each layer serves a specific function: the first layer (lower electron affinity) facilitates carrier injection, the second layer (higher electron affinity) provides high-mobility channel transport, and the third layer (lower electron affinity) enables carrier extraction. This segmentation resolves the contradiction by achieving improved electrical characteristics through functional division while managing device complexity through systematic layer design.
Solution Approach 2:
Different regions of the semiconductor layer are assigned different local qualities through the use of oxide semiconductor layers with varying electron affinities. The first and third layers have lower electron affinities optimized for carrier injection/extraction at electrode interfaces, while the second layer has higher electron affinity optimized for high-mobility transport in the channel region. This local quality differentiation achieves superior overall electrical characteristics while maintaining manageable device complexity through targeted material selection.
2Productivity
If device size is reduced for miniaturization, then integration density is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs a nested structure where the first, second, and third oxide semiconductor layers are stacked one within another in the vertical direction, with each layer positioned at different heights. The trenches are also nested within the insulating layer. This nesting approach enables miniaturization by utilizing the vertical dimension for layer integration, thereby increasing integration density while managing manufacturing precision requirements through a systematic stacked architecture.
Solution Approach 2:
The patent transitions from a planar semiconductor structure to a three-dimensional stacked structure by arranging oxide semiconductor layers in the vertical dimension. Multiple functional layers are stacked above and below each other, allowing the device to achieve higher integration density without proportionally increasing manufacturing precision requirements, as the vertical stacking provides an additional degree of freedom for design.
3Productivity
If high integration is achieved, then device density is improved, but impurity diffusion prevention becomes more difficult
Solution Approach 1:
Insulating layers are introduced as intermediary structures between the oxide semiconductor layers and other device components. These insulating layers act as diffusion barriers that prevent impurity diffusion while allowing the high-integration stacked structure to be maintained. The insulating layers are positioned strategically between the semiconductor layers and electrodes, providing protection against impurity contamination without compromising the compact integrated design.
Solution Approach 2:
The patent employs composite material structures combining oxide semiconductor layers with insulating layers in a stacked configuration. The oxide semiconductor layers provide high carrier mobility, while the insulating layers provide impurity diffusion prevention. This composite approach achieves both high integration density and reliable impurity protection by combining materials with complementary functions in a vertically stacked architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables the creation of miniaturized, highly integrated semiconductor devices with improved electrical characteristics and reliability by increasing carrier induction and reducing impurity diffusion, thus enhancing the performance and reliability of transistors and capacitors.
Implementation Method 1
oxide semiconductor layers with different electron affinities (or conduction band minimum states) are stacked to increase the carrier mobility of a transistor
Implementation Method 2
The first insulating layer and the third insulating layer are formed using a material having a high impurity barrier property, whereby diffusion of impurities from the outside to the oxide semiconductor layer can be prevented
Data Source
AI summary
A first trench and a second trench are formed in an insulating layer, a transistor including an oxide semiconductor layer in the first trench is formed, and a capacitor is formed along the second trench. A first gate electrode is formed over the first trench, and a second gate electrode is formed under the first trench.