Oxide Semiconductor Edge Contact for Low Cgd Capacitance
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Solution Overview
Problem
In semiconductor devices, particularly in liquid crystal panels, the use of oxide semiconductors like indium gallium zinc oxide leads to increased Cgd capacitance, which affects the applied voltage and deteriorates the performance of the semiconductor layer due to light exposure from backlights, especially when the gate metal size is reduced to minimize capacitance.
Innovation Solution
A semiconductor device configuration where an oxide semiconductor film with an etching stopper film is used, featuring a hole that exposes the edge portion of the semiconductor film, allowing the second electrode to cover and electrically connect with the edge portion, directing light-induced charges away from the semiconductor film, thereby reducing capacitance and minimizing performance deterioration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the gate metal size is decreased to reduce Cgd capacitance, then the Cgd capacitance is reduced, but the semiconductor layer becomes exposed to light from the backlight device causing performance deterioration
Solution Approach 1:
The patent introduces a light shielding layer as an intermediary component between the backlight device and the semiconductor layer. This light shielding layer selectively blocks light from reaching the semiconductor layer while allowing the gate metal to maintain its reduced size for low Cgd capacitance. The light shielding layer thus mediates between the conflicting requirements of capacitance reduction and semiconductor layer protection.
Solution Approach 2:
The patent segments the gate metal structure into multiple parts: the gate electrode that controls the semiconductor layer, and the light shielding layer that protects the semiconductor layer from light. This segmentation allows the gate metal to serve dual functions - electrical control and light blocking - enabling reduced gate metal size without compromising semiconductor layer protection.
2Speed
If oxide semiconductors are used instead of amorphous silicon, then electron mobility is improved, but Cgd capacitance increases affecting applied voltage
Solution Approach 1:
The patent changes the physical parameters of the gate metal structure, specifically reducing its area and optimizing its shape to minimize overlap with the source metal and semiconductor layer. This parameter change reduces the Cgd capacitance to acceptable levels while maintaining the high electron mobility benefits of oxide semiconductor materials.
3Area of stationary object
If the gate metal size is reduced to minimize capacitance, then the overlap area is decreased, but light from the backlight device reaches the semiconductor layer causing charge storage and performance deterioration
Solution Approach 1:
The light shielding layer serves as an intermediary that blocks light from reaching the semiconductor layer. This intermediary component decouples the relationship between gate metal size and light blocking function, allowing the gate metal to be minimized for low capacitance while the light shielding layer independently provides light protection.
Solution Approach 2:
The patent extracts the light blocking function from the gate metal structure and places it in a separate light shielding layer. This extraction allows the gate metal to focus solely on electrical control with minimized size, while the light shielding layer handles the light blocking function independently.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces Cgd capacitance and protects the oxide semiconductor film from light-induced damage, enhancing the overall performance and reliability of the semiconductor device.
Implementation Method 1
the gate metal causes the Cgd capacitance to be generated and also prevents (blocks) light exiting from a backlight device toward the liquid crystal panel (the TFT array board) from reaching the semiconductor layer
Implementation Method 2
If the light reaches the semiconductor layer and the semiconductor layer is exposed to the light, chemical reaction is caused in the semiconductor layer and charge storage occurs in the semiconductor layer
Data Source
AI summary
A semiconductor device 1 according to the present invention includes a first electrode G (g1) formed on a substrate B, a first insulation film GI to cover the first electrode g1, a semiconductor film SF including a channel CH, an etching stopper film ES, and a second electrode S (s3). The semiconductor film SF is formed on the first insulation film GI with overlapping the first electrode g1 so that an edge portion SF1 thereof projects outwardly from the first electrode g1 in a plan view. The etching stopper film ES is formed of an insulation film and formed on the semiconductor film SF and the first insulation film GI to cover the channel CH. The etching stopper film ES includes a hole H (hd) in which the edge portion SF1 of the semiconductor film SF is and through which a surface of a portion of the semiconductor film SF near the channel CH is exposed in a plan view. The second electrode S (s3) is disposed on the semiconductor film SF to cover the surface of the portion of the semiconductor film SF exposed through the hole H (hd).