Oxide Semiconductor End Region Layout for Parasitic Channel Suppression

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Solution Overview

Problem

In semiconductor devices using oxide semiconductors, the generation of parasitic channels in the end regions of the oxide semiconductor film leads to increased current consumption and voltage leakage due to stress from electric fields and impurity contamination during the manufacturing process.

Innovation Solution

The semiconductor device design includes a channel region formed between the side surfaces of the source and drain electrodes, with an end region of the oxide semiconductor film that does not overlap with the gate electrode, positioned between specific regions to prevent stress and impurity contamination, thereby suppressing parasitic channel formation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the oxide semiconductor film is formed with the entire end region overlapping the gate electrode, then the channel coverage is improved, but parasitic channels are generated in the end region due to electric field stress and impurity contamination

Engineering Contradiction:
Improvetransistor performance stabilityVSAvoidparasitic channel formation
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The invention extracts the problematic end region of the oxide semiconductor film from the area overlapping with the gate electrode. By designing the oxide semiconductor film to extend beyond the gate electrode width, the end regions are positioned in areas not affected by the gate electrode's electric field, thereby preventing parasitic channel formation while maintaining proper channel coverage in the overlapping region.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The invention applies different spatial configurations to different regions of the oxide semiconductor film. The central region overlaps with the gate electrode to form the active channel, while the end regions extend beyond the gate electrode boundaries to avoid electric field stress and impurity contamination, thus having different functional qualities in different locations.

Inventive Principle:
Principle #3Local quality

2Ease of manufacture

If the oxide semiconductor film end region is exposed to etching atmosphere during manufacturing, then the photolithography and etching processes can be completed, but the side surface is damaged and contaminated by impurities

Engineering Contradiction:
Improvephotolithography and etching process completionVSAvoidside surface integrity
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The invention extracts the end region of the oxide semiconductor film from the area that would be directly under the photoresist layer during photolithography. By extending the oxide semiconductor film beyond the gate electrode width, the end regions are positioned where photoresist is not formed, allowing them to be protected from etching atmosphere exposure while the central region undergoes normal photolithography and etching processes.

Inventive Principle:
Principle #2Taking out (Extraction)

3Reliability

If negative voltage is applied to the gate electrode during GBT stress test, then the transistor reliability is evaluated, but electric field stress activates the oxide semiconductor film and enhances its reactivity

Engineering Contradiction:
Improvetransistor reliability evaluationVSAvoidoxide semiconductor film conductivity stability
Core Design Contradiction:
ReliabilityVSStability of the object's composition

Solution Approach 1:

The invention extracts the end region of the oxide semiconductor film from the area overlapping with the gate electrode, where electric field stress would activate the film and enhance reactivity. By positioning end regions outside the gate electrode boundaries, they are excluded from the high electric field region during GBT stress testing, preventing activation and maintaining conductivity stability while still allowing reliability evaluation in the channel region.

Inventive Principle:
Principle #2Taking out (Extraction)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design effectively reduces the formation of parasitic channels, minimizing current consumption and voltage leakage, and enhancing the reliability of the semiconductor device.

Implementation Method 1

The oxide semiconductor film 1002 is activated by generation of electric field stress in the oxide semiconductor film 1002

Methodology Applied
Scientific EffectElectric field stress: Electric Field

Data Source

PatentUS9196743B2Field effect device with oxide semiconductor layer
Publication Date: 2015.11.24 SEMICON ENERGY LAB CO LTD
  • US9196743B2 patent drawing
  • US9196743B2 patent drawing
  • US9196743B2 patent drawing

AI summary

Provided is a semiconductor device in which generation of a parasitic channel in an end region of an oxide semiconductor film is suppressed. The semiconductor device includes a gate electrode, an oxide semiconductor film, a source electrode and a drain electrode, and a channel region formed in the oxide semiconductor film. The channel region is formed between a first side surface of the source electrode and a second side surface of the drain electrode opposite to the first side surface. The oxide semiconductor film has an end region which does not overlap with the gate electrode. The end region which does not overlap with the gate electrode is positioned between a first region that is the nearest to one end of the first side surface and a second region that is the nearest to one end of the second side surface.