Oxide-Semiconductor Dual Damascene Structure for Etch Protection
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Solution Overview
Problem
Oxide-semiconductor layers in semiconductor devices are vulnerable to damage and contamination during etching or cleaning processes, which can severely impact the electrical properties and performance of the devices.
Innovation Solution
A semiconductor device is designed with a lowered oxide-semiconductor layer and/or a protective insulating metal oxide layer formed on top, which prevents the oxide-semiconductor layer from being affected by later etching or cleaning processes. The device includes a substrate, a first metal layer, a first dielectric layer, a dual damascene metal structure, an oxide-semiconductor layer, and a metal oxide layer with at least two metal elements, where the top surface of the oxide-semiconductor layer is lower than the top surface of the first dielectric layer, and the metal oxide layer covers the oxide-semiconductor layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If oxide-semiconductor layer is exposed during etching or cleaning processes, then manufacturing process can proceed, but the oxide-semiconductor layer suffers damage and contamination affecting electrical properties
Solution Approach 1:
The patent applies preliminary action by lowering the oxide-semiconductor layer below the top surface of the first dielectric layer before subsequent etching or cleaning processes. This preparatory step ensures that the oxide-semiconductor layer is protected from damage and contamination during later manufacturing steps, allowing the process to proceed while maintaining electrical properties
Solution Approach 2:
The patent introduces a first dielectric layer as an intermediary protective structure between the oxide-semiconductor layer and the etching/cleaning processes. By lowering the oxide-semiconductor layer into this dielectric layer, the dielectric acts as a buffer that prevents direct exposure of the sensitive oxide-semiconductor to harmful processes
2Reliability
If oxide-semiconductor layer is lowered below dielectric surface, then protection from etching/cleaning is achieved, but additional processing steps are required
Solution Approach 1:
The lowering of the oxide-semiconductor layer is performed as a preliminary action before subsequent etching or cleaning processes. This single preparatory step establishes protection in advance, preventing the need for multiple protective measures during later processing steps
Solution Approach 2:
The patent combines the oxide-semiconductor layer formation with the dielectric layer structure, integrating the protective function into the existing layer architecture. The oxide-semiconductor layer is lowered into the first dielectric layer, merging the channel formation with the protective structure in a unified design
Data Source
AI summary
A semiconductor device is provided in present invention, including a substrate, a first metal layer on the substrate, a first dielectric layer on the first metal layer, a dual damascene metal structure through the first metal layer and the first dielectric layer and partly in the substrate, an oxide-semiconductor layer between the dual damascene metal structure and the first metal layer, and a metal oxide layer on the oxide-semiconductor layer and between the dual damascene metal structure and the oxide-semiconductor layer, wherein the top surface of oxide-semiconductor layer is lower than the top surface of first dielectric layer, the metal oxide layer includes at least two metal elements and covers the top surface of oxide-semiconductor layer.