Polycrystalline Oxide Semiconductor Layout for Etching Reliability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor devices using oxide semiconductors face challenges in achieving high field effect mobility and reliability due to issues with etching resistance and structural integrity, particularly in polycrystalline structures.
Innovation Solution
The semiconductor device incorporates a polycrystalline oxide semiconductor layer with specific edge regions of higher electrical resistivity, which are less susceptible to etching, and a manufacturing process that includes a heat treatment to crystallize the amorphous oxide semiconductor film, enhancing etching resistance and structural integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an oxide semiconductor film is used to achieve high field effect mobility, then the device can be manufactured by a low-temperature process with a simple structure, but the etching resistance is insufficient leading to edge regions being easily etched and reducing device reliability
Solution Approach 1:
The patent applies local quality by creating high-resistance regions specifically at the edge portions of the oxide semiconductor layer, while maintaining different properties in the central channel region. This is achieved by controlling the thickness of the oxide semiconductor layer to be greater than 5 nm in the central region and less than or equal to 5 nm at the edges, or by forming a separate high-resistance oxide semiconductor layer at the edges. This local differentiation provides enhanced etching resistance where needed without compromising the overall device performance.
Solution Approach 2:
The patent segments the oxide semiconductor layer into distinct regions with different thicknesses or resistivities - a central region with higher thickness for conduction and edge regions with lower thickness for etching resistance. This segmentation allows each region to fulfill its specific function: the central region maintains high field effect mobility while the edge regions provide protection against etching damage.
2Object-affected harmful factors
If the oxide semiconductor layer is made thinner to improve etching resistance, then edge regions become more resistant to etching, but the electrical performance and field effect mobility deteriorate
Solution Approach 1:
The patent implements local quality by assigning different thickness values to different spatial regions of the oxide semiconductor layer. The central channel region maintains a thickness greater than 5 nm to ensure adequate electrical performance and field effect mobility, while the edge portions are reduced to a thickness of less than or equal to 5 nm to provide etching resistance. This spatially differentiated thickness profile resolves the contradiction between etching resistance and electrical performance.
3Object-affected harmful factors
If heat treatment is applied to crystallize the amorphous oxide semiconductor film, then the etching resistance and structural integrity are enhanced, but heat-induced deterioration may occur in existing device structures
Solution Approach 1:
The patent applies preliminary action by performing heat treatment at a relatively low temperature (400°C to 600°C) for a controlled duration to partially crystallize the oxide semiconductor layer before subsequent processing steps. This preliminary crystallization enhances the etching resistance of the edge regions without subjecting the entire device structure to high temperatures that could cause deterioration. The controlled heat treatment prepares the oxide semiconductor layer for better etching performance while minimizing thermal damage to other device components.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution results in a semiconductor device with improved etching resistance, reduced heat-induced deterioration, and higher reliability by minimizing current paths in edge regions, thereby maintaining consistent electrical performance.
Implementation Method 1
An etching rate of the oxide semiconductor layer is less than 3 nm/min when the oxide semiconductor layer is etched using an etching solution containing phosphoric acid as a main component at 40° C.
Implementation Method 2
a manufacturing process that includes a heat treatment to crystallize the amorphous oxide semiconductor film
Data Source
AI summary
A semiconductor device includes a gate electrode, an oxide semiconductor layer having a polycrystalline structure, and a gate insulating layer between the gate electrode and the oxide semiconductor layer. The oxide semiconductor layer includes a source region and a drain region each containing an impurity element, a channel region between the source region and the drain region, and a first region adjacent to the channel region. The first region includes a first edge extending along a first direction travelling from the source region to the drain region. The first region has a higher electrical resistivity than each of the source region and the drain region. An etching rate of the oxide semiconductor layer is less than 3 nm/min when the oxide semiconductor layer is etched using an etching solution containing phosphoric acid as a main component at 40° C.