Amorphous Oxide Semiconductor FinFET Gate Control
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Solution Overview
Problem
Current oxide thin film transistors face challenges in achieving high performance and integration due to limitations in carrier mobility and channel layer properties, particularly in next-generation semiconductor circuits.
Innovation Solution
A semiconductor device design featuring a channel layer with an amorphous oxide semiconductor, where the channel layer's width is less than the gate electrode, and a tri-gate or gate-all-around structure is used, reducing resistance and enhancing drive current by forming a channel adjacent to the gate oxide layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the channel layer width is reduced to increase carrier mobility, then drive current improves, but leakage current increases
Solution Approach 1:
The patent transitions from a planar channel structure to a three-dimensional FinFET structure with vertical fins. This dimensional change allows the channel to extend vertically while maintaining a controlled top-down width, achieving both high carrier mobility through the vertical field effect and reduced leakage through the fin geometry that provides better gate control over the channel.
Solution Approach 2:
The channel layer is segmented into multiple vertical fins rather than a single planar channel. This segmentation creates multiple independent conduction paths, allowing the effective channel width to be reduced for lower leakage while maintaining drive current through the combined effect of multiple fins. The gate electrode wraps around these segmented fins to provide uniform control.
2Reliability
If the gate electrode width is increased to improve gate control, then drive current increases, but device area increases
Solution Approach 1:
The gate electrode extends vertically along the fins in addition to its horizontal span, creating a three-dimensional gate structure. This vertical extension provides enhanced gate control over the channel without requiring a proportional increase in horizontal device area. The gate wraps around the fins, utilizing the vertical dimension to increase control effectiveness while maintaining compact footprint.
Solution Approach 2:
The gate electrode is positioned to wrap around and enclose the vertical fins, with the fins nested within the gate's electrical field. This nested configuration maximizes gate control over the channel region while minimizing the overall device area, as the gate structure contains the active channel region rather than requiring additional lateral space.
3Productivity
If the channel length is shortened to increase drive current, then switching speed improves, but leakage current increases
Solution Approach 1:
The channel is extended into the vertical dimension through FinFET fins, creating a three-dimensional conduction path. This allows the effective channel length to be shortened horizontally for faster switching and higher drive current, while the vertical fin structure maintains adequate electrical length for leakage control. The gate's vertical wrap-around provides continuous control along the channel length.
Solution Approach 2:
The channel is divided into multiple vertical fin segments rather than a single continuous planar channel. This segmentation allows each fin to act as an independent conduction path with optimized length, achieving short effective lengths for high drive current while the combined structure provides sufficient total channel length for leakage control through the cumulative effect of multiple segments.
Data Source
AI summary
A semiconductor device includes a substrate, a gate electrode on the substrate, a channel layer between the substrate and the gate electrode, the channel layer including an amorphous oxide semiconductor, and a width of the gate electrode being greater than a width of the channel layer, a first conductive electrode connected to a first side surface of the channel layer, and a second conductive electrode connected to a second side surface of the channel layer.