Oxide Semiconductor Device With Gate Side Wall Channel Control
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Solution Overview
Problem
Semiconductor devices with channels made of amorphous silicon or low-temperature polysilicon have limitations in mobility and off-current, while those with single crystalline silicon have complex structures and high off-current, making them unsuitable for display devices, and oxide semiconductor devices require shorter channel lengths to achieve higher on-current but are restricted by photolithography mask sizes and substrate variance.
Innovation Solution
A semiconductor device structure with a gate electrode having a side wall, an oxide semiconductor layer along the side wall, a gate insulating layer between the electrode and the semiconductor layer, and insulating layers to control channel length and reduce variance, allowing for increased on-current and suppressed in-plane variance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the channel length is shortened to increase on-current in oxide semiconductor devices, then the on-current increases, but the manufacturing precision deteriorates due to photolithography mask size limitations and substrate in-plane variance
Solution Approach 1:
The patent replaces the photolithography-based mechanical patterning system with a self-aligned formation method using side walls of the gate electrode. The channel length is defined by the thickness of the gate insulating layer and the side wall dimensions rather than by photolithography mask patterns, eliminating the 2μm resolution limit and substrate variance issues inherent in photolithography.
Solution Approach 2:
The gate electrode side walls act as intermediary structures that define the channel length. Instead of directly patterning the source and drain regions to achieve short channel length, the side walls serve as中介 structures that enable precise channel length control through their thickness, which can be controlled independently of photolithography limitations.
2Ease of manufacture
If amorphous silicon is used for the channel to enable low-temperature processing on glass substrates, then the manufacturing complexity decreases and large substrate processing is enabled, but the mobility decreases making driving circuit usage impossible
Solution Approach 1:
The patent uses oxide semiconductor material (such as IGZO - indium gallium zinc oxide) as the channel layer, which combines the properties of both amorphous and crystalline semiconductors. This oxide semiconductor can be processed at low temperatures compatible with glass substrates while maintaining high carrier mobility comparable to crystalline silicon, thus resolving the contradiction between ease of manufacture and speed.
3Speed
If low-temperature polysilicon or single crystalline silicon is used for the channel to achieve high mobility for driving circuit usage, then the mobility increases enabling driving circuit application, but the off-current increases making it difficult to maintain applied voltage
Solution Approach 1:
The oxide semiconductor channel material combines the high mobility of crystalline silicon with the low off-current characteristics of amorphous silicon. The specific oxide semiconductor composition (e.g., IGZO) provides a high mobility-pathway while maintaining a large bandgap that suppresses off-current, thus resolving the contradiction between speed and harmful off-current effects.
Solution Approach 2:
The patent optimizes the local properties of the oxide semiconductor channel by controlling its composition, thickness, and crystalline structure in the channel region. This local optimization enables high mobility for on-state current while maintaining low off-state current through appropriate material engineering and interface control.
Data Source
AI summary
A semiconductor device includes a gate electrode having a first side wall at an end thereof, a gate insulating layer on a top surface and the first side wall of the gate electrode, an oxide semiconductor layer facing the first side wall, the gate insulating layer being between the first side wall and the oxide semiconductor layer, a first insulating layer on the oxide semiconductor layer, the oxide semiconductor layer being between the gate insulating layer and the first insulating layer, a first electrode connected with a first portion of the oxide semiconductor layer, and a second electrode connected with a second portion of the oxide semiconductor layer.