Oxide Semiconductor Layer Covering Gate Insulating Film Steps
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Solution Overview
Problem
In bottom-gate TFTs, the thinning of the gate insulating film reduces dielectric withstand voltage and exposes semiconductor layers to light, leading to reliability issues.
Innovation Solution
A display device with an oxide semiconductor layer that covers the step portions of the gate insulating film, forming a continuous transistor region and a separate covering region to prevent dielectric withstand voltage reduction and light exposure, along with a channel protective layer and passivation layer to enhance reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the gate insulating film is thinned during processing of the channel protective layer, then the processing can be completed, but the dielectric withstand voltage is reduced
Solution Approach 1:
The oxide semiconductor layer is formed in advance to cover the step portion of the gate insulating film before the channel protective layer processing. This preliminary action ensures that the gate insulating film thickness is maintained at the step portion, preventing dielectric withstand voltage reduction while allowing subsequent processing to proceed.
Solution Approach 2:
The oxide semiconductor layer acts as an intermediary protective layer that covers the step portion of the gate insulating film. This intermediary structure prevents direct exposure and thinning of the gate insulating film during channel protective layer processing, thereby maintaining dielectric withstand voltage while enabling process completion.
2Reliability
If the semiconductor layer is formed wider than the gate electrode to cover the step portion, then the dielectric withstand voltage is maintained, but light exposure accelerates semiconductor layer deterioration
Solution Approach 1:
The oxide semiconductor layer is segmented into two distinct regions: a transistor constituting region that contacts source and drain electrodes for device operation, and a covering region that covers the step portion of the gate insulating film to maintain dielectric withstand voltage. This segmentation allows the covering region to be isolated from light exposure while the transistor region maintains electrical functionality.
Solution Approach 2:
Different regions of the oxide semiconductor layer are assigned different functions: the transistor constituting region provides electrical conduction, while the covering region provides protective coverage of the gate insulating film step portion. This local differentiation allows the covering region to maintain dielectric withstand voltage without being exposed to light, as it is spatially separated from the light path.
3Object-affected harmful factors
If the semiconductor layer is located inside the periphery of the gate electrode, then light exposure is avoided, but the gate insulating film thickness is reduced during processing
Solution Approach 1:
The oxide semiconductor layer is extended into a third spatial dimension by forming a covering region that protrudes over the step portion of the gate insulating film. This dimensional extension allows the semiconductor layer to cover the step portion without being located inside the gate electrode periphery, thereby maintaining dielectric withstand voltage while avoiding light exposure through spatial separation.
Data Source
AI summary
A gate insulating film has a convex portion conforming to a surface shape of a gate electrode and a step portion that changes in height from a periphery of the gate electrode along the surface of the gate electrode. An oxide semiconductor layer is disposed on the gate insulating film so as to have a transistor constituting region having a channel region, a source region, and a drain region in a continuous and integral manner and a covering region being separated from the transistor constituting region and covering the step portion of the gate insulating film. A channel protective layer is disposed on the channel region of the oxide semiconductor layer. A source electrode and a drain electrode are disposed in contact respectively with the source region and the drain region of the oxide semiconductor layer. A passivation layer is disposed on the source electrode and the drain electrode.