Oxide Semiconductor Devices with Impurity-Diffused Insulation Layers
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Solution Overview
Problem
Conventional oxide semiconductor devices with inverted staggered structures face challenges in reducing the length of the active layer and increasing parasitic capacitance due to the alignment margin of the etch stop layer, leading to suboptimal electrical characteristics and reduced dimensions, which hinder the development of high-resolution and large-sized display devices.
Innovation Solution
The use of insulation layer patterns containing impurities, such as silicon oxyfluoride and silicon nitride, to form source and drain regions within the active layer, reducing channel length and parasitic capacitance by diffusing impurities like hydrogen or nitrogen through thermal treatment, thereby improving carrier mobility and contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If an etch stop layer is disposed on the channel region to form an inverted staggered structure, then the device structure is stabilized and etching is controlled, but the length of the active layer cannot be properly reduced due to alignment margin requirements
Solution Approach 1:
The invention extracts and removes the etch stop layer from the conventional inverted staggered structure. By eliminating this layer, the alignment margin requirement is removed, allowing the active layer length to be properly reduced without compromising manufacturing precision
Solution Approach 2:
The invention inverts the conventional structure by placing the gate electrode below the active layer without requiring an etch stop layer, fundamentally changing the stacking sequence and eliminating the alignment constraint that prevented active layer length reduction
2Object-generated harmful factors
If source and drain electrodes overlap side portions of the gate electrode below the etch stop layer, then the device structure is formed, but parasitic capacitance between the gate electrode, source electrode, and drain electrode is increased
Solution Approach 1:
By removing the etch stop layer, the invention eliminates the structural element that caused the source and drain electrodes to overlap with the gate electrode, thereby eliminating the source of parasitic capacitance without simplifying the overall device structure
Solution Approach 2:
The invention introduces insulation layer patterns with impurities (such as silicon oxyfluoride, silicon nitride, silicon oxynitride) that create regions of different electrical properties, effectively isolating the source and drain electrodes from the gate electrode to reduce parasitic capacitance
3Reliability
If the active layer length is not properly reduced, then the device dimensions are maintained, but the electrical characteristics and resolution of display devices are degraded
Solution Approach 1:
By extracting the etch stop layer, the invention enables the active layer length to be reduced to the desired dimension without the constraint of alignment margins, thereby improving electrical characteristics and enabling high-resolution display devices
Solution Approach 2:
The invention changes the structural parameters by removing the etch stop layer, which allows the active layer length parameter to be reduced while maintaining proper alignment and electrical characteristics
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in oxide semiconductor devices with improved electrical characteristics, including reduced contact resistance, decreased parasitic capacitance, increased carrier mobility, and enhanced driving current, enabling high-resolution and large-sized organic light emitting display devices with improved image quality and display rates.
Implementation Method 1
The source region and the drain region may include impurities diffused from the first insulation layer pattern and the second insulation layer pattern, respectively
Implementation Method 2
diffusing impurities like hydrogen or nitrogen through thermal treatment
Data Source
AI summary
An oxide semiconductor device includes a first insulation layer pattern and a second insulation layer pattern disposed on a substrate, an active layer disposed on the first and second insulation layer patterns, the active layer including a source region including the first insulation layer pattern, a drain region including the second insulation layer pattern, and a channel region disposed between the source and drain regions, a source electrode contacting the source region, and a drain electrode contacting the drain region.