Oxide Semiconductor Device With Impurity-Defined Regions
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Solution Overview
Problem
Existing semiconductor devices with oxide semiconductor films face challenges in achieving excellent electrical characteristics and manufacturing methods that result in small variations in electrical properties.
Innovation Solution
A method for manufacturing a semiconductor device involving the formation of an oxide semiconductor film with a gate insulating film, a gate electrode, and conductive films, where an impurity is added using ion doping or ion implantation to create regions with varying impurity concentrations, reducing resistance and enhancing electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a transistor is formed using an oxide semiconductor thin film, then the device can achieve low power consumption and compatibility with flexible substrates, but the electrical characteristics and uniformity show large variations
Solution Approach 1:
The patent applies local quality by creating distinct regions within the oxide semiconductor film with different impurity concentrations. A first region with lower impurity concentration (1×10^16 to 1×10^18 atoms/cm³) provides low off-state current, while a second region with higher impurity concentration (1×10^18 to 1×10^20 atoms/cm³) provides high on-state current. This spatial variation in material properties enables simultaneous optimization of both on and off states, resolving the contradiction between reliability and manufacturing precision.
Solution Approach 2:
The patent utilizes parameter changes by controlling impurity concentration as the key variable. Through ion implantation or ion doping processes, the impurity concentration is precisely adjusted to create the desired two-region structure. This parameter control allows the oxide semiconductor film to exhibit different electrical characteristics in different regions, achieving excellent and uniform electrical properties across devices.
2Reliability
If ion implantation or ion doping is used to add impurities to create conductive regions, then resistance is reduced and electrical performance is enhanced, but the process complexity increases
Solution Approach 1:
The patent applies preliminary action by performing ion implantation or ion doping at specific stages during the manufacturing process. The impurity addition is conducted after forming the oxide semiconductor film and before final device completion, allowing precise control over where and how impurities are introduced. This timing strategy enables creation of the desired conductive regions without requiring excessive process steps, balancing electrical performance improvement with process complexity management.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method produces a self-aligned semiconductor device with improved electrical characteristics and reduced variations, achieving high on-state current and stable electrical performance.
Implementation Method 1
adding an impurity to the pair of conductive films. The second region and the opening overlap with each other. The second region is formed by an impact caused by addition of the impurity to the pair of conductive films
Implementation Method 2
adding an impurity to the pair of conductive films. The second region and the opening overlap with each other. The second region is formed by an impact caused by addition of the impurity to the pair of conductive films
Implementation Method 3
performing planarization treatment on the interlayer insulating film; forming an opening in the interlayer insulating film subjected to the planarization treatment; forming a conductive film in the opening and over the interlayer insulating film subjected to the planarization treatment; forming a pair of conductive films by performing planarization treatment on the conductive film
Data Source
AI summary
A gate insulating film is formed over an oxide semiconductor film. A gate electrode is formed over the gate insulating film. An interlayer insulating film is formed over the oxide semiconductor film and the gate electrode. Planarization treatment is performed on the interlayer insulating film. An opening is formed in the interlayer insulating film subjected to the planarization treatment. A conductive film is formed in the opening and over the interlayer insulating film subjected to the planarization treatment. A pair of conductive films is formed by performing planarization treatment on the conductive film. A first region and a second region are formed in the oxide semiconductor film by adding an impurity to the pair of conductive films. The second region and the opening overlap with each other. The second region is formed by an impact caused by addition of the impurity to the pair of conductive films.