Three-Layer Oxide Semiconductor Structure for Reduced Interface Scattering
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Solution Overview
Problem
The electrical characteristics of transistors with oxide semiconductor layers are degraded due to interface scattering and trap levels at the interface between the oxide semiconductor layer and the insulating film, leading to reduced field-effect mobility and reliability.
Innovation Solution
A semiconductor device structure is implemented with a stack of three oxide semiconductor layers, where the second oxide semiconductor layer is not in contact with a silicon-containing gate insulating film, and the energy band diagram is optimized to reduce interface states, using a CAAC-OS film with specific atomic ratios and deposition conditions to enhance carrier flow and reduce oxygen vacancies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single oxide semiconductor layer is used in contact with silicon-containing gate insulating film, then device structure is simple, but interface scattering and trap levels degrade field-effect mobility
Solution Approach 1:
The oxide semiconductor layer is divided into three distinct layers: a first oxide semiconductor layer in contact with the gate insulating film, a second oxide semiconductor layer with higher carrier concentration serving as the channel formation region, and a third oxide semiconductor layer. This segmentation isolates the high-carrier-concentration channel region from direct contact with the gate insulating film, reducing interface scattering and trap level effects while maintaining structural organization.
Solution Approach 2:
The first and third oxide semiconductor layers act as intermediary layers between the silicon-containing gate insulating film and the second oxide semiconductor layer. These intermediary layers prevent direct contact between the channel formation region and the gate insulating film, thereby reducing interface states and improving field-effect mobility without requiring complete elimination of the gate insulating film structure.
2Reliability
If oxide semiconductor layer contacts silicon-containing gate insulating film, then manufacturing process is simple, but trap levels cause electrical characteristic degradation
Solution Approach 1:
The oxide semiconductor layer is divided into three distinct layers: a first oxide semiconductor layer in contact with the gate insulating film, a second oxide semiconductor layer with higher carrier concentration serving as the channel formation region, and a third oxide semiconductor layer. This segmentation isolates the high-carrier-concentration channel region from direct contact with the gate insulating film, reducing interface scattering and trap level effects while maintaining structural organization.
Solution Approach 2:
The first oxide semiconductor layer is formed in advance as a protective barrier between the gate insulating film and the channel formation region. This preliminary layer prevents trap levels from forming at the critical interface, ensuring electrical characteristic stability before the channel formation region is completed.
3Reliability
If interface between oxide semiconductor and insulating film is reduced, then field-effect mobility improves, but device structure becomes more complex
Solution Approach 1:
The oxide semiconductor layer is divided into three distinct layers: a first oxide semiconductor layer in contact with the gate insulating film, a second oxide semiconductor layer with higher carrier concentration serving as the channel formation region, and a third oxide semiconductor layer. This segmentation isolates the high-carrier-concentration channel region from direct contact with the gate insulating film, reducing interface scattering and trap level effects while maintaining structural organization.
Solution Approach 2:
The first, second, and third oxide semiconductor layers are merged into a unified stacked structure that functions as a complete channel formation region. This merging maintains overall structural simplicity while internally optimizing the interface characteristics through the three-layer configuration, achieving high field-effect mobility without excessive complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This structure achieves high field-effect mobility and reliability by minimizing interface scattering and trap levels, resulting in improved electrical characteristics and reduced photodegradation.
Implementation Method 1
using a CAAC-OS film with specific atomic ratios and deposition conditions to enhance carrier flow and reduce oxygen vacancies
Data Source
AI summary
The electrical characteristics of a transistor including an oxide semiconductor layer are varied by influence of an insulating film in contact with the oxide semiconductor layer, that is, by an interface state between the oxide semiconductor layer and the insulating film. A first oxide semiconductor layer S1, a second oxide semiconductor layer S2, and a third oxide semiconductor layer S3 are sequentially stacked, so that the oxide semiconductor layer through which carriers flow is separated from the gate insulating film containing silicon. The thickness of the first oxide semiconductor layer S1 is preferably smaller than those of the second oxide semiconductor layer S2 and the third oxide semiconductor layer S3, and is less than or equal to 10 nm, preferably less than or equal to 5 nm.