Oxide Semiconductor Layer Lattice Matching for TFT Stability
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Solution Overview
Problem
The oxide semiconductor layer in array substrates does not match the gate insulating layer at the contact interface, leading to unstable properties and undesirable effects such as threshold voltage shift due to interface defects.
Innovation Solution
A method for manufacturing an array substrate involving the formation of a semiconductor layer with a first insulative oxide layer and a second semiconductive oxide layer, where the first oxide layer is located between the gate insulating layer and the second oxide layer, and the second oxide layer is converted into a conductor using plasma treatment, with an insulative oxide layer acting as a protection layer to alleviate interface defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If an oxide semiconductor layer is used as the active layer in TFT, then high mobility and large size product applicability are improved, but unstable properties and threshold voltage shift occur due to lattice mismatch with gate insulating layer
Solution Approach 1:
An insulative oxide layer is introduced as an intermediary between the gate insulating layer and the oxide semiconductor layer. This intermediate layer has a lattice structure that matches both the gate insulating layer and the oxide semiconductor layer, thereby reducing interface defects and preventing charge trapping that would otherwise cause threshold voltage shift, while allowing the oxide semiconductor to maintain its high mobility properties
2Device complexity
If a single oxide semiconductor layer is formed, then manufacturing process is simplified, but interface defects with gate insulating layer cause unstable device properties
Solution Approach 1:
The semiconductor layer is segmented into two distinct oxide layers: a lower insulative oxide layer that interfaces with the gate insulating layer and provides lattice matching, and an upper semiconductive oxide layer that provides the necessary electrical properties. This segmentation resolves the contradiction by allowing each layer to optimize its function while maintaining manufacturing simplicity through a single formation process
3Manufacturing precision
If multiple patterning processes are used to form active layer and pixel electrode, then manufacturing precision is improved, but manufacturing cost and process complexity increase
Solution Approach 1:
The oxide semiconductor layer serves multiple functions: it acts as both the active layer of the TFT and the pixel electrode material. By forming a single patterned oxide layer that fulfills both roles, the invention eliminates the need for separate patterning processes, thereby reducing manufacturing cost and process complexity while maintaining the required precision through proper material selection and single-step patterning
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces interface defects and undesirable effects by matching the lattice structure of the insulative oxide layer with the semiconductive oxide layer, allowing for a single patterning process to form the active layer and pixel electrode, thereby reducing manufacturing costs and improving substrate stability.
Implementation Method 1
subjecting the second oxide layer in the pixel electrode region to plasma treatment, to convert the second oxide layer in the pixel electrode region into a conductor
Implementation Method 2
forming a first oxide film using a sputtering process, where a gas used in the sputtering process includes oxygen and argon
Data Source
AI summary
A method for manufacturing an array substrate, an array substrate and a display panel are provided. The method includes forming patterns of a gate metal layer and a gate insulating layer successively on a base plate, forming a pattern of a semiconductor layer, where the pattern of the semiconductor layer comprises a pattern of an active region and a pattern of a pixel electrode region, the semiconductor layer comprises an insulative oxide layer and a semiconductive oxide layer stacked on the insulative oxide layer, and the insulative oxide layer is located between the gate insulating layer and the semiconductive oxide layer, forming a pattern of a source and drain metal layer, and subjecting the semiconductive oxide layer in the pixel electrode region to plasma treatment, to convert the semiconductive oxide layer in the pixel electrode region into a conductor.