Oxide Semiconductor Transistor for Low-Leakage Memory
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Solution Overview
Problem
Conventional semiconductor devices, such as DRAM and SRAM, face challenges with short data retention times and high power consumption due to leakage currents, while flash memory experiences degradation from tunneling currents and requires high voltage for data retention, limiting their suitability for frequent data rewriting.
Innovation Solution
A semiconductor device is developed using a highly-purified oxide semiconductor with a stacked structure of transistors, where one transistor includes an oxide semiconductor and another includes a material other than oxide semiconductor, reducing leakage current and eliminating the need for high voltage, allowing for long-term data retention without refresh operations and unlimited rewriting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of moving object
If a DRAM structure with transistor and capacitor is used, then writing and reading operations can be performed, but data retention time is short due to leakage current and refresh operations are needed
Solution Approach 1:
The invention changes the material parameter of the transistor from conventional semiconductor to oxide semiconductor, which fundamentally alters the electrical characteristics to achieve extremely low leakage current and long data retention without refresh operations
Solution Approach 2:
The invention uses a composite structure combining oxide semiconductor layer with conventional semiconductor substrate, integrating the low-leakage properties of oxide semiconductor with the成熟 manufacturing processes of conventional semiconductor devices
2Duration of action of moving object
If SRAM with flip-flop circuit is used, then data retention time is extended without refresh operation, but cost per storage capacity increases
Solution Approach 1:
The invention changes the transistor material to oxide semiconductor, which enables long data retention with a simple 1-transistor structure, avoiding the complex flip-flop circuitry of SRAM while achieving similar or better retention characteristics
3Duration of action of moving object
If flash memory with floating gate is used, then data retention time is extremely long and refresh operation is not needed, but gate insulating layer deteriorates due to tunneling current
Solution Approach 1:
The invention changes from floating gate structure to oxide semiconductor transistor structure, eliminating the need for high-voltage tunneling current while achieving long data retention through the inherent low-leakage properties of oxide semiconductor
Solution Approach 2:
The invention removes the floating gate component entirely, extracting the problematic tunneling current mechanism while retaining the desired non-volatile memory functionality through oxide semiconductor-based charge trapping
4Duration of action of moving object
If flash memory structure is used, then data retention is achieved, but high voltage is required for writing and erasing operations
Solution Approach 1:
The invention changes the material properties of the transistor to oxide semiconductor, which enables low-voltage operation while maintaining long data retention, eliminating the high-voltage requirement of flash memory
5Speed
If conventional semiconductor transistor is used, then high-speed operation is achieved, but leakage current is high causing short data retention
Solution Approach 1:
The invention creates a composite device structure combining oxide semiconductor transistor with conventional semiconductor components, achieving both high-speed operation from the transistor channel and long data retention from the low-leakage oxide semiconductor properties
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables extended data retention with minimal power consumption, high-speed operation, and no limitations on the number of writing cycles, improving reliability and reducing the need for additional storage devices.
Implementation Method 1
The low off current of the second transistor allows the data stored in the memory cell to be retained for a significantly long time even in the absence of supply of electric power
Data Source
Figure 1A~1B
Figure 2A~2D
Figure 3A1~3B
AI summary
A first transistor including a channel formation region, a first gate insulating layer, a first gate electrode, and a first source electrode and a first drain electrode; a second transistor including an oxide semiconductor layer, a second source electrode and a second drain electrode, a second gate insulating layer, and a second gate electrode; and a capacitor including one of the second source electrode and the second drain electrode, the second gate insulating layer, and an electrode provided to overlap with one of the second source electrode and the second drain electrode over the second gate insulating layer are provided. The first gate electrode and one of the second source electrode and the second drain electrode are electrically connected to each other.