Oxide Semiconductor Memory Cell 3D Stacking Integration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor devices face challenges in achieving miniaturization, high integration, high operation speed, favorable electrical characteristics, small variation in transistor electrical characteristics, and low power consumption while maintaining reliability.
Innovation Solution
A semiconductor device with a structure that includes a first insulator, a second insulator, and memory cells comprising a first transistor and a first capacitor. The first transistor has an oxide semiconductor layer, conductors, and insulators arranged in specific openings and layers to enhance performance and integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a plurality of memory cells are overlapped by stacking transistors to achieve higher density integration, then the integration density is improved, but the manufacturing complexity and process difficulty increase
Solution Approach 1:
The patent implements three-dimensional stacking of memory cells by forming transistor layers (first transistor 200a, second transistor 200b) and capacitor layers (first capacitor 100a, second capacitor 100b) in vertical stacking over the substrate. This vertical arrangement in the third dimension enables higher integration density without proportionally increasing lateral footprint or manufacturing complexity
Solution Approach 2:
The memory device is divided into discrete functional blocks: first memory cell containing first transistor 200a and first capacitor 100a, second memory cell containing second transistor 200b and second capacitor 100b. Each transistor is segmented into gate electrode 260, source/drain electrodes 242a/242b, and oxide semiconductor layer 230, allowing independent formation and optimization of each component
2Length of moving object
If transistor size is reduced to achieve miniaturization, then the device size is reduced, but the electrical characteristics and reliability deteriorate
Solution Approach 1:
The transistor employs an oxide semiconductor layer 230 (such as In-Ga-Zn-O) as the active channel material, which provides superior electrical characteristics including low leakage current and high mobility compared to conventional semiconductors. This composite material approach maintains reliability while enabling miniaturization to transistor sizes of 72 nm and below
Solution Approach 2:
The patent implements a dual-gate transistor structure with gate electrode 260 and back gate electrode 205, allowing dynamic control of the channel conductivity through independent voltage application to each gate. This dynamic control capability maintains electrical characteristics and reliability even as transistor dimensions are reduced
3Loss of energy
If oxide semiconductor transistors are used to reduce leakage current, then power consumption is reduced, but the on-state current and operation speed are limited
Solution Approach 1:
The oxide semiconductor layer 230 composition is optimized with specific atomic ratios (In:Ga:Zn = 1:1:1 to 1:3:4) and controlled thickness (5 nm to 50 nm) to achieve the desired balance between low leakage current in the off-state and high on-state current. The band gap and carrier concentration are tuned through compositional control to simultaneously reduce leakage and enhance drive current
Solution Approach 2:
The dual-gate configuration enables independent control of threshold voltage and channel conductivity through voltage application to gate electrode 260 and back gate electrode 205. This dynamic control allows the transistor to achieve high on-state current when needed while maintaining low leakage current when the channel is closed, thereby improving both power efficiency and operation speed
Data Source
AI summary
A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes a first insulator, a second insulator over the first insulator, and a memory cell including a transistor and a capacitor. The transistor includes an oxide over the first insulator, a first conductor and a second conductor over the oxide, a third insulator over the oxide, and a third conductor over the third insulator. The third insulator and the third conductor are located in a first opening of the second insulator. The capacitor includes a fourth conductor in contact with a top surface of the second conductor, a fourth insulator over the fourth conductor, and a fifth conductor over the fourth insulator. The fourth conductor, the fourth insulator, and the fifth conductor are located in a second opening of the second insulator. A third opening is formed in the first insulator, the second insulator, and the first conductor. A sixth conductor is located in the third opening. The sixth conductor includes a region in contact with part of a top surface of the first conductor and part of a side surface of the first conductor in each of a plurality of layers.