Oxide Semiconductor Memory Cell Verification
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Solution Overview
Problem
Current semiconductor memory devices face challenges in accurately detecting defective memory cells with shorter data holding times due to the time-consuming nature of existing verification methods, which increases manufacturing costs.
Innovation Solution
The implementation of a memory device structure that includes a first capacitor with significantly higher capacitance than a second capacitor, allowing for charge storage and verification operations to be performed efficiently, along with the use of transistors with oxide semiconductors having wider band gaps and lower intrinsic carrier densities to minimize off-state current and extend data holding times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a general verification method is used where data is read immediately after data is written, then the verification operation is fast, but it cannot accurately detect memory cells with short data holding times because the digital value has not changed yet
Solution Approach 1:
The patent applies preliminary action by performing a write operation to store data in the memory cell before the verification operation. This ensures that the data is properly stored and the digital value has had time to change, allowing accurate detection of defective memory cells with short holding times. The write operation precedes the read operation, creating the necessary temporal separation for accurate measurement.
Solution Approach 2:
The patent introduces dynamic control of the verification timing by making the verification operation configurable rather than fixed. The verification can be performed at different time points after writing, allowing the system to adapt to different data holding times. This dynamic approach enables accurate detection of both normal and defective memory cells by adjusting the verification timing based on the specific memory cell characteristics.
2Measurement precision
If the verification operation time is extended to accurately detect defective memory cells, then detection accuracy improves, but manufacturing cost increases
Solution Approach 1:
The patent changes the temporal parameter of the verification operation by introducing a configurable delay between write and read operations. Instead of using a fixed immediate read, the verification can be delayed to allow sufficient time for data stabilization in memory cells with short holding times. This parameter adjustment enables accurate detection without requiring excessive verification time, thereby controlling manufacturing costs while improving detection accuracy.
3Reliability
If transistors with oxide semiconductors are used, then off-state current is reduced and data holding time is extended, but device complexity increases
Solution Approach 1:
The patent changes the material parameter of the transistor by using oxide semiconductors with wider band gaps and lower intrinsic carrier densities. This material substitution fundamentally improves the off-state current characteristics and extends data holding times. The oxide semiconductor layer is formed between the gate electrode and the source/drain regions, creating a transistor structure that achieves superior electrical characteristics while maintaining reasonable manufacturing complexity through established deposition techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables accurate and rapid detection of defective memory cells, reducing manufacturing costs and improving the reliability of semiconductor devices by allowing for quicker verification of data holding times and minimizing charge leakage.
Implementation Method 1
transistors with oxide semiconductors having wider band gaps and lower intrinsic carrier densities to minimize off-state current
Implementation Method 2
transistors with oxide semiconductors having wider band gaps and lower intrinsic carrier densities to minimize off-state current
Implementation Method 3
a first capacitor with significantly higher capacitance than a second capacitor, allowing for charge storage and verification operations to be performed efficiently
Data Source
AI summary
To provide a memory device which can perform verification operation for detecting a memory cell whose data holding time is shorter than a predetermined length, accurately in a short time. Each memory cell includes at least a first capacitor, a second capacitor, and a transistor which functions as a switching element for controlling supply, storage, and release of charge in the first capacitor and the second capacitor. The capacitance of the first capacitor is thousand or more times the capacitance of the second capacitor, preferably ten thousand or more times the capacitance of the second capacitor. In normal operation, charge is stored using the first capacitor and the second capacitor. In performing verification operation for detecting a memory cell whose data holding time is shorter than a predetermined length, charge is stored using the second capacitor.