Oxide Semiconductor Memory Cell with Dual-Gate Transistor Structure
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Solution Overview
Problem
Current DRAM memory devices require frequent refresh operations to prevent data loss due to charge leakage, leading to increased power consumption and destruction of written data during read operations.
Innovation Solution
A memory device structure incorporating a first and second transistor with oxide semiconductor channel formation regions, where the second transistor's gate electrode is directly connected to its second electrode, allowing for reduced off-state current and enabling data retention without destroying written data, thus reducing the frequency of refresh operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a simple DRAM structure with transistor and capacitor is used, then storage capacity per unit area is increased and cost is reduced, but data is lost during read operation and refresh operation must be repeated frequently
Solution Approach 1:
The invention divides the memory cell into two distinct transistors: a first transistor for write operation and a second transistor for data retention. This segmentation allows each transistor to perform its specific function independently, enabling non-destructive read operations while maintaining simple cell structure for high density.
Solution Approach 2:
The second gate electrode of the second transistor serves as an intermediary charge storage node. By controlling the potential of this gate electrode, data can be retained without requiring a separate capacitor, and read operations can be performed by detecting potential changes without destroying the stored data.
2Reliability
If flash memory with floating gate is used for nonvolatile storage, then data retention is improved, but high voltage of about 20V is required leading to increased power consumption
Solution Approach 1:
The invention changes the operating voltage parameters by using standard low-voltage transistor operations instead of high-voltage floating gate operations. The second transistor's gate electrode is controlled at low voltages, eliminating the need for 20V programming pulses while achieving nonvolatile data retention through the unique transistor structure and oxide semiconductor material.
Solution Approach 2:
The invention uses oxide semiconductor materials for the channel formation regions of both transistors. This composite material approach combines the benefits of low-power operation (like DRAM) with nonvolatile data retention (like flash memory), creating a hybrid memory cell that operates at low voltage while maintaining data without frequent refreshes.
3Reliability
If DRAM refresh operation is repeated frequently to prevent data loss, then data retention is maintained, but power consumption is increased
Solution Approach 1:
The second transistor structure with its unique dual-gate configuration enables the memory cell to maintain data autonomously without external refresh operations. The oxide semiconductor material's properties allow the cell to retain data indefinitely at room temperature, making the cell self-sufficient for data retention and eliminating the power-consuming refresh cycle.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed memory device design reduces power consumption by minimizing the need for frequent refresh operations while allowing data to be read without destruction, thereby lowering overall power usage and extending data retention time.
Implementation Method 1
The first channel formation region and the second channel formation region contain an oxide semiconductor
Data Source
AI summary
The first transistor includes first and second electrodes which are a source and a drain, and a first gate electrode overlapping with a first channel formation region with an insulating film provided therebetween. The second transistor includes third and fourth electrodes which are a source and a drain, and a second channel formation region which is provided between a second gate electrode and a third gate electrode with insulating films provided between the second channel formation region and the second gate electrode and between the second channel formation region and the third gate electrode. The first and second channel formation regions contain an oxide semiconductor, and the second electrode is connected to the second gate electrode.