Oxide Semiconductor Memory Cell With Low-Off-Current Data Storage
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Solution Overview
Problem
Current memory devices, such as DRAM and flash memory, face challenges in power consumption, data retention, and durability due to leakage currents, high voltage requirements, and limitations in the number of writing operations.
Innovation Solution
A semiconductor device with a layered structure incorporating a transistor using an oxide semiconductor and another material, where the oxide semiconductor transistor has extremely low off current, allowing for long-term data retention without the need for refresh operations and high-speed operation without voltage limitations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a transistor is used in a DRAM memory element, then data can be stored in a capacitor, but leakage current causes short data holding time and requires frequent refresh operations increasing power consumption
Solution Approach 1:
The patent changes the material parameter of the transistor from conventional semiconductor to oxide semiconductor, which fundamentally alters the electrical characteristics to achieve extremely low off-state current. This parameter change enables data to be held without refresh operations, simultaneously improving data holding time and reducing power consumption.
2Duration of action of stationary object
If a floating gate is used in flash memory to store data, then data holding time becomes extremely long, but tunneling current deteriorates the gate insulating layer limiting the number of writing operations
Solution Approach 1:
The patent extracts and eliminates the floating gate structure from the memory element, replacing it with a conventional gate transistor using oxide semiconductor. This removes the source of tunneling current that causes gate insulating layer deterioration, enabling unlimited writing operations while maintaining non-volatile data storage capability.
3Reliability
If high voltage is applied to inject charge to the floating gate, then data can be written, but it takes relatively long time and limits writing speed
Solution Approach 1:
The patent changes the voltage parameter from high voltage to low voltage operation by eliminating the floating gate structure. The oxide semiconductor transistor enables efficient charge control at low voltages, dramatically improving writing speed while maintaining reliable data storage.
4Reliability
If a flip-flop circuit is used in SRAM to retain data, then refresh operation is not needed, but cost per storage capacity increases
Solution Approach 1:
The patent creates a composite memory structure combining oxide semiconductor material with conventional semiconductor materials. This enables the use of simpler transistor structures instead of complex flip-flop circuits, reducing device complexity and cost while achieving non-volatile data retention.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables reduced power consumption, high-speed data reading and writing, and increased durability by eliminating the need for refresh operations and minimizing gate insulating film deterioration, allowing for an unlimited number of writing cycles.
Implementation Method 1
the oxide semiconductor transistor has extremely low off current, allowing for long-term data retention without the need for refresh operations
Implementation Method 2
a gate insulating layer over the channel formation region
Data Source
AI summary
Disclosed is a semiconductor device capable of functioning as a memory device. The memory device comprises a plurality of memory cells, and each of the memory cells contains a first transistor and a second transistor. The first transistor is provided over a substrate containing a semiconductor material and has a channel formation region in the substrate. The second transistor has an oxide semiconductor layer. The gate electrode of the first transistor and one of the source and drain electrodes of the second transistor are electrically connected to each other. The extremely low off current of the second transistor allows the data stored in the memory cell to be retained for a significantly long time even in the absence of supply of electric power.