Oxide Semiconductor Memory Cell Array With Internal Driver Circuit
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor memory devices face challenges in increasing writing and reading speed while maintaining reliability, as miniaturization leads to decreased storage capacitance and increased power consumption due to higher refresh operation frequencies, and the increased number of wirings results in defects and larger chip sizes.
Innovation Solution
A memory device design where the potential is supplied to word lines and data lines from within the cell array, using a driver circuit to reduce wiring resistance and employing transistors with a wide-bandgap semiconductor material like oxide semiconductors to minimize off-state current and leakage, thereby reducing refresh operations and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the area of memory cell is reduced to increase memory capacity per unit area, then storage capacitance is decreased, but this requires increased refresh operation frequency which increases power consumption and reduces reliability
Solution Approach 1:
The patent changes the material parameter of the transistor from conventional semiconductor to oxide semiconductor, which fundamentally alters the off-state current characteristics. This material parameter change enables maintaining adequate storage capacitance even with reduced memory cell area, thereby avoiding the need for increased refresh frequency and reducing power consumption.
Solution Approach 2:
The patent applies different material qualities to different parts of the memory device. Specifically, oxide semiconductor transistors are used in memory cells where low off-state current is critical, while other parts of the device may use conventional materials. This localized application of superior material properties solves the contradiction between miniaturization and power consumption.
2Area of stationary object
If the area of memory cell is reduced to increase memory capacity per unit area, then storage capacitance is decreased, but this requires increased refresh operation frequency which reduces reliability due to transistor deterioration
Solution Approach 1:
The patent changes the material parameter of the transistor from conventional semiconductor to oxide semiconductor, which fundamentally alters the off-state current characteristics. This material parameter change enables maintaining adequate storage capacitance even with reduced memory cell area, thereby avoiding the need for increased refresh frequency and reducing reliability degradation from frequent refresh operations.
3Speed
If the number of wirings is increased to maintain memory cell ratio, then writing and reading speed is improved, but this increases the area of cell array and reduces yield due to defects
Solution Approach 1:
The patent changes the electrical parameter of the transistor (off-state current) by using oxide semiconductor material. This parameter change allows for reduced wiring width and spacing while maintaining signal integrity, thereby reducing the total number of wirings needed and increasing yield without sacrificing speed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances writing and reading speeds, reduces refresh operations, and maintains reliability by minimizing off-state current and power consumption, while allowing for a smaller device size and increased storage capacitance per unit area.
Implementation Method 1
a potential generated at a driver circuit is supplied to a wiring such as a word line or a data line not from the outside of the cell array but from the inside of the cell array or between two memory cells
Implementation Method 2
employing transistors with a wide-bandgap semiconductor material like oxide semiconductors to minimize off-state current and leakage
Implementation Method 3
data is stored by supply of electric charge to a capacitor
Data Source
AI summary
To provide a memory device which operates at high speed or a memory device in which the frequency of refresh operations is reduced. In a cell array, a potential is supplied from a driver circuit to a wiring connected to a memory cell. The cell array is provided over the driver circuit. Each of memory cells included in the cell array includes a switching element, and a capacitor in which supply, holding, and discharge of electric charge are controlled by the switching element. Further, a channel formation region of the transistor used as the switching element includes a semiconductor whose band gap is wider than that of silicon and whose intrinsic carrier density is lower than that of silicon.