Oxide Semiconductor Memory Circuit with Feedback Loop for Data Retention
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Solution Overview
Problem
Existing memory circuits face challenges in retaining data after power is turned off due to high power consumption and limited rewriting operations, particularly with ferroelectric elements and flash memory, which suffer from degradation and fatigue, making them unsuitable for frequent power interruptions.
Innovation Solution
A memory circuit design incorporating a transistor with extremely low off-state current, a capacitor, and arithmetic circuits that form a feedback loop, allowing data to be held even after power is stopped by using a transistor with a wider band gap semiconductor and a switch to manage data transfer and storage efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a ferroelectric element is used in the memory circuit to store data after power is stopped, then data retention capability is improved, but the number of rewriting operations is limited due to ferroelectric material fatigue
Solution Approach 1:
The memory circuit is divided into two distinct parts: a volatile memory unit (flip-flop circuit) for frequent data storage and retrieval, and a nonvolatile memory unit for data retention after power stop. This segmentation allows each part to optimize its function without the limitations of using a single memory type for both purposes.
Solution Approach 2:
A transistor with extremely low off-state current is introduced as an intermediary component to control data transfer between the volatile and nonvolatile memory units. This transistor acts as a mediator that enables efficient data migration while maintaining the advantages of both memory types.
2Reliability
If data is transferred to an external memory unit to prevent data loss during long power stop, then data retention is improved, but it takes a long time for returning data from the external memory unit
Solution Approach 1:
The nonvolatile memory unit is nested within the volatile memory unit structure, with the transistor with extremely low off-state current serving as a shared resource. This nested configuration allows rapid data transfer between the two memory units without requiring external memory interfaces, significantly reducing data retrieval time while maintaining data retention capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces power consumption by allowing data to be retained for a long period without degradation, increasing the number of rewriting operations and enabling rapid data retrieval upon power restart, thus enhancing the reliability and efficiency of signal processing circuits.
Implementation Method 1
a transistor whose off-state current is extremely low
Data Source
AI summary
A memory circuit includes a transistor having a channel in an oxide semiconductor layer, a capacitor, a first arithmetic circuit, a second arithmetic circuit, a third arithmetic circuit, and a switch. An output terminal of the first arithmetic circuit is electrically connected to an input terminal of the second arithmetic circuit. The input terminal of the second arithmetic circuit is electrically connected to an output terminal of the third arithmetic circuit via the switch. An output terminal of the second arithmetic circuit is electrically connected to an input terminal of the first arithmetic circuit. An input terminal of the first arithmetic circuit is electrically connected to one of a source and a drain of the transistor. The other of the source and the drain of the transistor is electrically connected to one of a pair of electrodes of the capacitor and to an input terminal of the third arithmetic circuit.