Oxide Semiconductor Memory Cell Reducing Leakage Current
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Solution Overview
Problem
Conventional content addressable memories have large circuit areas and short data holding periods due to high leakage current, leading to increased power consumption and the need for continuous power supply or additional storage.
Innovation Solution
A memory device with a reduced number of transistors, utilizing a transistor with low off-state current and an oxide semiconductor layer, which compares stored data with search data to determine content, reducing circuit area and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional SRAM memory circuits are used, then data storage and comparison functions are achieved, but circuit area becomes large
Solution Approach 1:
The patent extracts and removes unnecessary transistors from the conventional SRAM structure. Specifically, it eliminates the need for six transistors by using only three transistors (first, second, and third transistors) to achieve the same storage and comparison functions, thereby reducing circuit area while maintaining reliability
Solution Approach 2:
The memory cell circuit is designed to perform multiple functions using a reduced number of transistors. The first transistor handles both data storage and comparison operations, while the second and third transistors enable comparison with search data, allowing the circuit to achieve both storage and comparison capabilities without requiring separate dedicated circuits for each function
2Duration of action of stationary object
If conventional transistors with high leakage current are used, then circuit area is reduced, but data holding period becomes short due to leakage current
Solution Approach 1:
The patent changes the key parameter of the transistor - specifically selecting a transistor with low off-state current (leakage current). The first transistor is chosen to have an off-state current of 10 aA/μm or less, which fundamentally alters the energy loss characteristic and enables long data holding periods without requiring additional power supply or backup memory
3Duration of action of stationary object
If transistors with low off-state current are used, then data holding period is extended, but manufacturing difficulty increases
Solution Approach 1:
The patent employs oxide semiconductor materials (such as indium gallium zinc oxide) to form the transistor channel. These composite oxide semiconductor materials inherently exhibit extremely low off-state currents (10 aA/μm or less) while being compatible with standard semiconductor manufacturing processes, thus achieving both long data holding periods and ease of manufacture
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution reduces circuit area and power consumption while extending data holding periods without the need for additional capacitors, enabling efficient data storage and comparison.
Implementation Method 1
a first transistor having an off-state current per micrometer of channel width of lower than or equal to 10 aA and controlling writing of the first data by being in an on state and holding of the first data by being in an off state
Data Source
AI summary
A memory cell includes a first transistor controlling writing of the first date by being in an on state, and holding of the first data by being in an off state, a second transistor in which a potential of one of a source and a drain is a potential of the second data and a potential of a gate is a potential of the first data, and a third transistor which has a conductivity type opposite to that of the second transistor, which has one of a source and a drain electrically connected to the other of the source and the drain of the second transistor, and in which a potential of a gate is a potential of the first data.