Oxide Semiconductor Memory Cell for Low Leakage Multilevel Storage

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Solution Overview

Problem

Conventional semiconductor memory devices using silicon substrates face challenges in storing multilevel data due to high leakage and large circuit area, which affects retention characteristics and efficiency.

Innovation Solution

A semiconductor memory device utilizing a memory cell with an oxide semiconductor substrate, including a select transistor and a capacitance element, that stores charge corresponding to coupling weights, enabling multilevel data storage with improved retention and reduced leakage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a silicon substrate is used in a conventional semiconductor memory device, then the device can store data, but it suffers from high leakage and large circuit area which deteriorates retention characteristics

Engineering Contradiction:
Improveretention characteristicsVSAvoidleakage
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The patent changes the material parameter of the substrate from silicon to oxide semiconductor, which fundamentally alters the electrical characteristics. This material substitution reduces leakage current by several orders of magnitude while maintaining the memory function, directly resolving the contradiction between reliability and energy loss.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent employs a composite structure combining oxide semiconductor substrate with metal electrodes (such as tungsten or copper) and insulation films. This composite approach leverages the low-leakage property of oxide semiconductors while using metals for high-conductivity connections, optimizing both retention characteristics and circuit performance.

Inventive Principle:
Principle #40Composite materials

2Productivity

If a silicon substrate is used in a conventional semiconductor memory device, then the device can store data, but it requires large circuit area which reduces efficiency

Engineering Contradiction:
Improvestorage efficiencyVSAvoidcircuit area
Core Design Contradiction:
ProductivityVSArea of stationary object

Solution Approach 1:

By changing the substrate material to oxide semiconductor, the patent achieves higher charge retention capability per unit area. This allows for more efficient use of circuit area, as each memory cell can maintain its state longer without requiring larger storage capacitors or refresh circuits, thereby improving storage efficiency.

Inventive Principle:
Principle #35Parameter changes

3Quantity of substance

If multilevel data storage is implemented using conventional silicon-based memory, then data capacity increases, but leakage and circuit area increase which degrades performance

Engineering Contradiction:
Improvedata capacityVSAvoidretention characteristics
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The oxide semiconductor substrate enables multilevel data storage by providing distinct, stable charge states that can represent multiple data levels. The material's inherent low-leakage property ensures that each charge level is maintained reliably over time, allowing high data capacity without sacrificing retention characteristics.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The memory device effectively stores multilevel data with high retention characteristics and reduced leakage, suppressing the increase in circuit area, thus providing a high-quality memory solution.

Implementation Method 1

a capacitance element configured to store a charge

Methodology Applied
Scientific EffectCapacitance: Capacitance

Implementation Method 2

a transistor formed of an oxide semiconductor

Methodology Applied
Scientific EffectOxide semiconductor properties:

Data Source

PatentUS10431287B2Semiconductor memory device including a memory cell with first and second transistors
Publication Date: 2019.10.01 KIOXIA CORP
  • US10431287B2 patent drawing
  • US10431287B2 patent drawing
  • US10431287B2 patent drawing

AI summary

According to one embodiment, a semiconductor memory device includes a memory cell including a transistor formed of an oxide semiconductor, an insulation film, and a control electrode, and a capacitance element configured to store a charge, the memory cell being configured to store a coupling weight of a neuron model by a charge amount accumulated in the capacitance element; and a control circuit configured to output a signal as a sum of a product between input data of the memory cell and the coupling weight.