Oxide Semiconductor Memory Element for Power-Stop Data Retention
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Solution Overview
Problem
Current signal processing circuits face issues with data retention during power stoppages due to ferroelectric material fatigue and high voltage requirements in flash memory, leading to limited rewriting times and slow data transfer between volatile and external memory devices.
Innovation Solution
A memory element comprising transistors with extremely small off-state current, using semiconductor materials with wider bandgaps, such as oxide or nitride semiconductors, to store signals and reduce the need for frequent data rewriting, combined with a sense amplifier and precharge circuit for efficient data reading and writing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If ferroelectric material is used for memory element, then data retention during power stop is achieved, but writing error increases due to material fatigue from repetition of data writing
Solution Approach 1:
The patent changes the fundamental parameter of charge storage from ferroelectric material polarization to transistor gate voltage. By using transistors with extremely small off-state current (such as oxide semiconductor transistors), the memory element can retain data without material fatigue, eliminating the writing error problem while maintaining retention capability.
Solution Approach 2:
The patent employs composite transistor structures using oxide semiconductor materials (such as In-Ga-As oxide semiconductors) which combine wide bandgap properties with low off-state current characteristics. This composite material approach enables both long retention time and high reliability by avoiding the fatigue issues of ferroelectric materials.
2Duration of action of stationary object
If flash memory is used for non-volatile storage, then data retention during power stop is achieved, but memory element deterioration occurs due to high voltage requirements for tunnel current generation
Solution Approach 1:
The patent changes the operating parameter from high voltage tunnel current (flash memory) to low voltage gate control (transistor-based memory). By using transistors with extremely small off-state current, the memory can retain data without applying high voltages, thus avoiding memory element deterioration and extending durability.
Solution Approach 2:
The patent replaces the physical tunneling mechanism of flash memory with an electrical field-based transistor switching mechanism. This substitution eliminates the need for high voltage stress, reducing mechanical and electrical deterioration of memory elements while maintaining non-volatile storage capability.
3Reliability
If data is transferred to external memory device during power stop, then data retention is maintained, but data return time increases significantly
Solution Approach 1:
The patent creates a copy of the volatile memory's storage mechanism using transistor gate voltages that can be maintained during power stop. This copy allows data to be retained locally without transferring to external memory, eliminating the time loss associated with external memory transfers while maintaining data retention reliability.
Solution Approach 2:
The patent performs preliminary action by writing data to the transistor-based memory structure before power stop occurs. The extremely small off-state current of the transistors ensures data is retained during power stop without requiring external memory transfer, and data can be immediately read after power restoration, eliminating transfer time delays.
4Speed
If volatile memory is used for register or cache, then high-speed data writing is achieved, but data is erased when power supply is stopped
Solution Approach 1:
The patent uses composite transistor structures with oxide semiconductor materials that combine the fast switching capability needed for high-speed writing with the extremely small off-state current required for data retention during power stop. This composite approach resolves the contradiction between speed and retention.
Solution Approach 2:
The patent changes the key parameter of transistor off-state current to an extremely small value using oxide semiconductor materials. This parameter change enables the memory to retain data during power stop while maintaining the fast writing speed characteristic of volatile memory, as the transistors can still switch rapidly when powered.
Data Source
AI summary
A memory element having a novel structure and a signal processing circuit including the memory element are provided. A first circuit, including a first transistor and a second transistor, and a second circuit, including a third transistor and a fourth transistor, are included. A first signal potential and a second signal potential, each corresponding to an input signal, are respectively input to a gate of the second transistor via the first transistor in an on state and to a gate of the fourth transistor via the third transistor in an on state. After that, the first transistor and the third transistor are turned off. The input signal is read out using both the states of the second transistor and the fourth transistor. A transistor including an oxide semiconductor in which a channel is formed can be used for the first transistor and the third transistor.