Oxide Semiconductor Memory Circuits for Refresh-Free Retention
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Solution Overview
Problem
Existing volatile and non-volatile semiconductor memory devices face limitations such as high power consumption, data loss when power is off, limited writing operations, and slow writing/erasing speeds, necessitating complex circuits and high voltages.
Innovation Solution
A semiconductor device with a multilayered structure comprising transistors made of both oxide and non-oxide semiconductors, where the oxide semiconductor transistor has extremely low off-state current, allowing data retention without power and high-speed operation, while the non-oxide semiconductor transistor enables fast data reading.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a DRAM structure with transistor and capacitor is used, then writing speed is fast, but power consumption is high due to frequent refresh operations
Solution Approach 1:
The patent segments the semiconductor device into two distinct functional regions: a first region with high-leakage transistors optimized for fast writing operations, and a second region with low-leakage transistors optimized for data retention. This segmentation allows each region to be optimized for its specific function without compromising the other, resolving the contradiction between fast writing (requiring high-speed transistors) and low power consumption (requiring minimal leakage current).
Solution Approach 2:
The patent applies local quality by using different transistor types in different locations within the same device. The first region uses transistors with higher leakage current characteristics for fast writing, while the second region uses transistors with extremely low leakage current for data retention. This spatial differentiation of transistor properties allows the device to simultaneously achieve fast writing speed and low power consumption during data holding.
2Duration of action of stationary object
If a flash memory structure with floating gate is used, then data holding time is long, but the number of writing operations is limited due to gate insulating layer deterioration
Solution Approach 1:
The patent divides the memory device into two separate regions with different transistor characteristics. The first region handles frequent writing operations using transistors that can withstand higher stress, while the second region maintains data using transistors with extremely low leakage for long-term retention. This segmentation allows the device to achieve both long data holding time and high reliability for repeated writing operations by distributing the functional demands across different regions.
Solution Approach 2:
The patent changes the key parameter of transistor leakage current between the two regions. The first region uses transistors with higher leakage current that can tolerate frequent writing, while the second region uses transistors with extremely low leakage current (1×10^-21 A or less) for stable data retention. This parameter differentiation resolves the contradiction between durability for repeated writing and stability for long-term data holding.
3Duration of action of stationary object
If an SRAM structure with flip-flop circuit is used, then refresh operation is not needed, but cost per storage capacity is increased
Solution Approach 1:
The patent segments the memory cell into two functional parts: a first region that handles writing operations and a second region that maintains data retention. By using low-leakage transistors in the second region, the device achieves data retention without requiring complex refresh circuits like DRAM or flip-flop structures like SRAM. This segmentation allows simpler circuitry while maintaining the benefits of both DRAM (simplicity) and SRAM (no refresh needed).
Solution Approach 2:
The patent applies local quality by placing low-leakage transistors specifically in the data retention region while using standard transistors in the writing region. This localized application of low-leakage characteristics eliminates the need for complex refresh operations throughout the entire device, reducing overall circuit complexity while maintaining data retention capabilities.
4Reliability
If high voltage is applied to inject electric charge in floating gate, then data can be stored, but writing and erasing speed is slow
Solution Approach 1:
The patent segments the charge storage function between two regions: the first region handles fast charge injection and removal for writing operations, while the second region maintains charges with extremely low leakage for long-term storage. This segmentation eliminates the need for high-voltage tunneling operations required by flash memory, as the low-leakage transistors in the second region can retain charges at standard voltages, thereby improving both writing speed and energy efficiency.
Solution Approach 2:
The patent changes the voltage parameter from high voltage (required for flash memory tunneling) to standard voltage operation. The low-leakage transistors in the second region are capable of retaining charges at standard voltages due to their extremely low off-state current, eliminating the need for high-voltage stress operations and enabling faster, lower-power writing and erasing operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The device achieves long-term data retention without refresh operations, reduces power consumption, eliminates the need for high voltages, and allows high-speed data writing and reading, overcoming the limitations of existing technologies.
Implementation Method 1
the second transistor includes an oxide semiconductor layer... the off-state current of the second transistor is 1×10^-21 A or less
Data Source
AI summary
It is an object to provide a semiconductor having a novel structure. In the semiconductor device, a plurality of memory elements are connected in series and each of the plurality of memory elements includes first to third transistors thus forming a memory circuit. A source or a drain of a first transistor which includes an oxide semiconductor layer is in electrical contact with a gate of one of a second and a third transistor. The extremely low off current of a first transistor containing the oxide semiconductor layer allows storing, for long periods of time, electrical charges in the gate electrode of one of the second and the third transistor, whereby a substantially permanent memory effect can be obtained. The second and the third transistors which do not contain an oxide semiconductor layer allow high-speed operations when using the memory circuit.